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參數(shù)資料
| 型號： | LC78624E |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Compact Disc Player DSP(用于CD播放器的8位DSP) |
| 中文描述： | 光碟機(jī)的DSP（用于光盤播放器的8位數(shù)字信號處理器） |
| 文件頁數(shù)： | 8/27頁 |
| 文件大?。?/td> | 357K |
| 代理商： | LC78624E |
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No. 5811-8/27
LC78624E
Continued from preceding page.
Pin No.
Symbol
I/O
Function
51
SBCK
I
Subcode readout clock input. This is a Schmitt input. (Must be connected to 0 V when unused.)
52
FSX
O
Output for the 7.35 kHz synchronization signal divided from the crystal oscillator
53
WRQ
O
Subcode Q output standby output
54
RWC
I
Read/write control input. This is a Schmitt input.
55
SQOUT
O
Subcode Q output
56
COIN
I
Command input from the control microcontroller
57
CQCK
I
Input for both the command input clock and the subcode readout clock. This is a Schmitt input.
58
RES
I
Chip reset input. This pin must be set low briefly after power is first applied.
59
TST11
O
Test output. Leave open. (Normally outputs a low level.)
60
16M
O
16.9344 MHz output.
61
4.2M
O
4.2336 MHz output
62
TEST5
I
Test input. A pull-down resistor is built in. Must be connected to 0 V.
63
CS
I
Chip select input. A pull-down resistor is built in. Must be connected to 0 V if not controlled.
64
TEST1
I
Test input. No pull-down resistor. Must be connected to 0 V.
Note: The same potential must be supplied to all power supply pins, i.e., V
DD
, VV
DD
and XV
DD
.
Pin Applications
1. HF Signal Input Circuit; Pin 10: EFMIN, pin 9: EFMO, pin 1: DEFI, pin 12: CLV
+
An EFM signal (NRZ) sliced at an optimal level can be
acquired by inputting the HF signal to EFMIN.
The LC78624E handles defects as follows. When a high level is
input to the DEFI pin (pin 1), EFMO (pin 9) pins (the slice level
control outputs) go to the high-impedance state, and the slice
level is held. However, note that this function is only valid in
CLV phase control mode, that is, when the V/P pin (pin 14) is
low. This function can be used in combination with the
LA9230M, and LA9240M DEF pins.
Note: If the EFMIN and CLV
+
signal lines are too close to
each other, unwanted radiation can result in error rate
degradation. We recommend laying a ground or V
DD
shield line between these two lines.
2. PLL Clock Generation Circuit; Pin 3: PDO, pin 5: ISET, pin 7: FR, pin 21: PCK
Since the LC78624E includes a VCO circuit, a PLL circuit can
be formed by connecting external R and C (resistors and
capacitors). ISET is the charge pump reference current, PDO is
the VCO circuit loop filter, and FR is a resistor that determines
the VCO frequency range.
(Reference values)
R1 = 68 k
, C1 = 0.1 μF
R2 = 680
, C2 = 0.1 μF
R3 = 1.2 k
The V
CO
×
2 command is an auxiliary command for characteristics guarantee in low-voltage operations. This
command supports the low-voltage operations at V
DD
= 3.0 to 3.6 V.
Code
COMMAND
VCO
×
2 SET
VCO
×
1 SET
RES = low
$AC
$AD
G
G
A09900
A09901
Frequency
phase
comparator
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LC78625E | SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs |
| LC78625 | SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs |
| LC78626KE | Compact Disc Player DSP(用于CD播放器的8位DSP) |
| LC78626 | 16-bit fixed point DSP with Flash |
| LC78626E | 16-bit fixed point DSP with Flash |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC78625 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Compact Disc Player DSP |
| LC78625E | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Compact Disc Player DSP |
| LC78626 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:DSP for Compact Disk Players |
| LC78626E | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:DSP for Compact Disk Players |
| LC78626KE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CD-Player Processor/Controller |
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