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參數(shù)資料
| 型號： | LC78624E |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Compact Disc Player DSP(用于CD播放器的8位DSP) |
| 中文描述： | 光碟機的DSP（用于光盤播放器的8位數(shù)字信號處理器） |
| 文件頁數(shù)： | 17/27頁 |
| 文件大?。?/td> | 357K |
| 代理商： | LC78624E |
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Note: 1. When the desired track count has been input in binary, the track check operation is started by the fall of RWC.
2. During a track check operation the TOFF pin goes high and the tracking loop is turned off. Therefore, feed motor forwarding is required.
3. When a track check in/out command is issued the function of the WRQ signal switches from the normal mode subcode Q standby monitor function
to the track check monitor function. This signal goes high when the track check is half completed, and goes low when the check finishes. The
microcontroller should monitor this signal for a low level to determine when the track check completes.
4. If a two-byte reset command is not issued, the track check operation will repeat. That is, to skip over 20,000 tracks, issue a track check 201
command once, and then count the WRQ signal 100 times. This will check 20,000 tracks.
5. After performing a track check operation, use the brake command to have the pickup lock onto the track.
8. Error Flag Output; Pin 48: EFLG, pin 52: FSX
The FSX signal is generated by dividing the crystal oscillator clock, and is a 7.35 kHz frame synchronization signal.
The error correction state for each frame is output from EFLG. The FSX low-level period indicates the C1 correction
state, and the high-level period indicates the C2 correction state. The playback OK/NG state can be easily determined
from the extent of the high level that appears here.
9. Subcodes P, Q and R to W Output Circuit; Pin 49: PW, pin 47: SBSY, pin 50: SFSY, pin 51: SBCK
PW is the subcode signal output pin, and all the codes, P, Q, and R to W can be read out by sending eight clocks to
the SBCK pin within 136 μs after the fall of SFSY. The signal that appears on the PW pin changes on the rising edge
of SBCK. SFSY is a signal that is output for each subcode frame cycle, and the falling edge of this signal indicates
standby for the output of the subcode symbol (P to W). Subcode data P is output on the fall of this signal. However,
when the text data is read or reset, subcodes cannot be read because the LC78624E is in the text mode. The subcodes
can be read by inputting the SW1P ON command.
SBSY is a signal output for each subcode block. This signal goes high for the S0 and S1 synchronization signals. The
fall of this signal indicates the end of the subcode synchronization signals and the start of the data in the subcode
block. (EIAJ format)
No. 5811-17/27
LC78624E
Code
Command
RES = low
$4E
SW1P OFF
G
G
$4F
SW1P ON
A09914
A09915
A09916
相關(guān)PDF資料 |
PDF描述 |
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| LC78625E | SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs |
| LC78625 | SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs |
| LC78626KE | Compact Disc Player DSP(用于CD播放器的8位DSP) |
| LC78626 | 16-bit fixed point DSP with Flash |
| LC78626E | 16-bit fixed point DSP with Flash |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC78625 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Compact Disc Player DSP |
| LC78625E | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Compact Disc Player DSP |
| LC78626 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:DSP for Compact Disk Players |
| LC78626E | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:DSP for Compact Disk Players |
| LC78626KE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CD-Player Processor/Controller |
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