參數(shù)資料
型號(hào)： LC72146V
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
封裝： SSOP-24
文件頁(yè)數(shù)： 9/22頁(yè)
文件大小： 157K
代理商： LC72146V
Charge Pump
The charge pump configuration is shown in Figure 9.
Figure 9 Charge Pump
When unlock is detected following a channel change, PDS (the sub-charge pump) operates. The value of R1 changes to
R1M // R1S (R1S
≈ 100 ), as shown in Figure 10, decreasing the low-pass filter time-constant and accelerating PLL
locking.
Figure 10 Charge Pump Connections
No. 4922-17/22
LC72146, 72146M, 72146V
PDC1
PDC0
PDS (sub-charge pump state)
0
—
High impedance
1
Charge pump operates (normal operation)
1
0
Charge pump operates (when unlocked)
DLC
PD1, PD0, PDS
0
Normal operation
1
Forced to low
PD1
PD0
A IN
PDS
R1S
DO, I/O-5 pin
PDC1
Unlock
Detector
and
Subcharge
Pump Cont.
Phase
Detector
Clock
fref
fvco/N
UL0
DZ0
DZ1
DLC
UL1
PDC0
R1S = 100
(typ)
(SUB)
(MAIN)
A OUT
PDO
PDS
R1S
R1M
V tune
VCC
相關(guān)PDF資料
PDF描述
LC72146M PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
LC72147V PLL FREQUENCY SYNTHESIZER, 180 MHz, PDSO24
LC72148V PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
LC72191M PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
LC7730M PULSE; RECTANGULAR, TIMER, PDSO16
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