參數(shù)資料
型號: LC72146V
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
封裝: SSOP-24
文件頁數(shù): 18/22頁
文件大?。?/td> 157K
代理商: LC72146V
Continued from preceding page.
Pin Assignment
Block Diagram
No. 4922-5/22
LC72146, 72146M, 72146V
Parameter
Symbol
Conditions
min
typ
max
Unit
Output off leakage current
IOFF1
I/O-1 to I/O3, AOUT, O-7; VO = 13 V
5.0
A
IOFF2
DO; VO = 6.5 V
5.0
A
High-level three state
IOFFH
PD0, PD1, AIN; VO = VDD
0.01
200
nA
off leakage current
Lowh-level three state
IOFFL
PD0, PD1, AIN; VO = 0 V
0.01
200
nA
off leakage current
Input cacitance
CIN
FMIN
6
pF
Pull-down transistor
Rpd1
FMIN
80
200
600
k
on resistance
Rpd2
AMIN
80
200
600
k
VDD; Xtal = 7.2 MHz, fIN2 = 160 MHz,
IDD1
VIN2 = 70 mVrms, fIN4 = 25 MHz
10
15
mA
Supply current
VIN4 = 40 mVrms
IDD2
VDD; PLL inhibited,
0.5
1.5
mA
crystal oscillator running (Xtal = 7.2 MHz)
IDD3
VDD; PLL inhibited, crystal oscillator stoped
10
A
Top View
LC72146, 72146M, 72146V
24
XIN
23
V
SS
22
A
OUT
21
AIN
20
PD0
19
PD1
18
V
SS
17
FMIN
16
AMIN
15
V
DD
14
HCTR/I-6
13
LCTR/I-7
1
XOUT
2
CE
3
DI
4
CL
5
DO
6
O-7
7
O-6
8
I/O-5
9
I/O-4
10
I/O-3
11
I/O-2
12
I/O-1
Top View
REFERENCE
DIVIDER
24
1
17
18
16
2
3
4
5
15
23
20
19
14
13
21
22
12
11
10
9
8
7
6
UNIVERSAL
COUNTER
PHASE DETECTOR
CHARGE PUMP
SWALLOW COUNTER
1/16, 1/17, 4bits
CCB
I/F
12bits PROGRAMMABLE
DIVIDER
DATA SHIFT REGISTER
LATCH
POWER
ON
RESET
XIN
XOUT
FMIN
VSS
AMIN
CE
DI
CL
DO
VDD
VSS
PD1
PD0
HCTR/I-6
LCTR/I-7
AIN
AOUT
I/O-1
I/O-2
I/O-3
I/O-4
I/O-5
O-6
O-7
相關(guān)PDF資料
PDF描述
LC72146M PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
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