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參數(shù)資料
| 型號： | LC66E5316 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Four-Bit Single-Chip Microcontroller with 16 KB of On-Chip EPROM |
| 中文描述： | 四位單片機與16 KB的片上存儲器控制器 |
| 文件頁數(shù)： | 24/27頁 |
| 文件大?。?/td> | 201K |
| 代理商： | LC66E5316 |
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Continued from preceding page.
No. 5488-24/27
LC66E5316
Instruction code
Affected
status
bits
Mnemonic
Operation
Description
Note
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
[Jump and subroutine instructions]
Store the contents of reg in
M2 (SP). Subtract 2 from SP
after the store.
PUSH
reg
Push reg on M2 (SP)
1 1 0 0
1 1 1 1
1 1 1 1
1 i
1
i
0
0
2
2
M2 (SP)
←
(reg)
SP
←
(SP) – 2
Add 2 to SP and then load the
contents of M2(SP) into reg.
The relation between i1i0 and
reg is the same as that for the
PUSH reg instruction.
POP
reg
1 1 0 0
1 1 1 0
1 1 1 1
1 i
1
i
0
0
SP
←
(SP) + 2
reg
←
[M2 (SP)]
Pop reg off M2 (SP)
2
2
Return from
subroutine
SP
←
(SP) + 4
PC
←
[M4 (SP)]
Return from a subroutine or
interrupt handling routine. ZF
and CF are not restored.
RT
0 0 0 1
1 1 0 0
1
2
Return from interrupt
routine
SP
←
(SP) + 4
PC
←
[M4 (SP)]
CF, ZF
←
[M4 (SP)]
Return from a subroutine or
interrupt handling routine. ZF
and CF are restored.
RTI
0 0 0 1
1 1 0 1
1
2
ZF, CF
[Branch instructions]
PC7 to 0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if (AC, t2) = 1
PC7 to 0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if (AC, t2) = 0
PC7 to 0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if [M (HL),t2]
= 1
PC7 to 0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if [M (HL),t2]
= 0
Branch to the location in the
same page specified by P
7
to
P
0
if the bit in AC specified by
the immediate data t
1
t
0
is one.
Branch to the location in the
same page specified by P
7
to
P
0
if the bit in AC specified by
the immediate data t
1
t
0
is zero.
Branch to the location in the
same page specified by P
7
to
P
0
if the bit in M (HL) specified
by the immediate data t
1
t
0
is one.
BAt2
addr
Branch on AC bit
1 1 0 1
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
0 0 t
1
t
0
2
2
BNAt2
addr
Branch on no AC bit
1 0 0 1
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
0 0 t
1
t
0
2
2
BMt2
addr
1 1 0 1
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
0 1 t
1
t
0
Branch on M bit
2
2
Branch to the location in the
same page specified by P
7
to
P
0
if the bit in M (HL) specified
by the immediate data t
1
t
0
is zero.
BNMt2
addr
1 0 0 1
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
0 1 t
1
t
0
Branch on no M bit
2
2
Internal control
registers can also
be tested by
executing this
instruction
immediately after
a BANK
instruction.
However, this is
limited to
registers that can
be read out.
PC7 to 0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if [P (DP
L
), t2]
= 1
Branch to the location in the
same page specified by P
7
to
P
0
if the bit in port (DP
L
)
specified by the immediate
data t
1
t
0
is one.
BPt2
addr
Branch on Port bit
1 1 0 1
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
1 0 t
1
t
0
2
2
Internal control
registers can also
be tested by
executing this
instruction
immediately after
a BANK
instruction.
However, this is
limited to
registers that can
be read out.
PC7 to 0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if [P (DP
L
), t2]
= 0
Branch to the location in the
same page specified by P
7
to
P
0
if the bit in port (DP
L
)
specified by the immediate
data t
1
t
0
is zero.
BNPt2
addr
Branch on no Port bit
1 0 0 1
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
1 0 t
1
t
0
2
2
N
b
N
c
Continued on next page.
reg
i
1
0
0
1
1
i
0
0
1
0
1
HL
XY
AE
Illegal value
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