參數(shù)資料
型號： LC66E5316
廠商： Sanyo Electric Co.,Ltd.
英文描述： Four-Bit Single-Chip Microcontroller with 16 KB of On-Chip EPROM
中文描述： 四位單片機(jī)與16 KB的片上存儲器控制器
文件頁數(shù)： 17/27頁
文件大?。?/td> 201K
代理商： LC66E5316
Continued from preceding page.
Note: 1. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. These pins cannot be used as input pins if the
CMOS output specifications are selected.
2. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. The rating for the pull-up output specification pins is
stipulated in terms of the output pull-up current IPO. These pins cannot be used as input pins if the CMOS output specifications are selected.
3. With the output Nch transistor off for CMOS output specification pins. (Also applies when the Pch open-drain option is selected for P8.)
4. With the output Nch transistor off for pull-up output specification pins.
5. When CMOS output specifications are selected for P8.
6. With the output Nch transistor off for pull-up output specification pins.
7. With the output Pch transistor off for open-drain output specification pins.
8. Reset state
Comparator Characteristics
at Ta = –30 to +70°C, V
SS
= 0 V
Note: 1. Does not include the quantization error.
Figure 1 External Clock Input Waveform
No. 5488-17/27
LC66E5316
Parameter
Symbol
Conditions
min
typ
max
Unit
Note
[Serial output]
SO0, SO1: With the timing of Figure 5 and
the test load of Figure 5. Stipulated with respect
to the falling edge (
↓
) of SCK0 or SCK1.
Output delay time
t
CKO
0.3
μs
[Pulse conditions]
INT0: Figure 6, conditions under which the INT0
interrupt can be accepted, conditions under
which the timer 0 event counter or pulse width
measurement input can be accepted
INT0 high and low-level
t
IOH
, t
IOL
2
Tcyc
High and low-level pulse widths
for interrupt inputs other than INT0
t
IIH
, t
IIL
INT1, INT2: Figure 6, conditions under which
the corresponding interrupt can be accepted
2
Tcyc
PIN1 high and low-level
pulse widths
t
PINH
, t
PINL
PIN1: Figure 6, conditions under which the
timer 1 event counter input can be accepted
2
Tcyc
RES high and low-level
pulse widths
t
RSH
, t
RSL
RES: Figure 6, conditions under which reset
can be applied.
3
Tcyc
Operating current drain
I
DD OP
V
DD
: 4-MHz ceramic oscillator
V
DD
: 4-MHz external clock
V
DD
: 4-MHz ceramic clock
V
DD
: 32 kHz (main oscillator stopped),
sub-oscillator: crystal
6.0
12
mA
8
6.0
12
mA
4
8
mA
Halt mode current drain
I
DDHALT
100
500
μA
Hold mode current drain
I
DDHOLD
V
DD
: V
DD
= 1.8 to 5.5 V
0.01
10
μA
Parameter
Symbol
Conditions
min
typ
max
Unit
Note
Absolute precision
V
CECM
V
THCM
V
INCM
T
CCM
AN1 to AN4: V
DD
= 4.5 to 5.5 V
V
DD
= 4.5 to 5.5 V
AN1 to AN4: V
DD
= 4.5 to 5.5 V
V
DD
= 4.5 to 5.5 V
±1/2
±1
LSB
1
Threshold voltage
V
SS
V
SS
V
DD
V
DD
30
V
Input voltage
V
Conversion time
μs
textL
OPEN
(OSC2)
OSC1
textR
1/fext
textF
VSS
VDD
0.2VDD
0.8VDD
textH
External clock
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