
Continued from preceding page.
Electrical Characteristics
at Ta = –30 to + 70°C, V
SS
= 0 V, V
DD
= 3.0 to 5.5 V unless otherwise specified
Note: 1. Common input and output ports with open-drain output specifications are specified for the state with the output N-channel transistor turned off.
These pins cannot be used for input when the CMOS output specification option is selected.
2. Common input and output ports with open-drain output specifications are specified for the state with the output N-channel transistor turned off.
Ratings for pull-up output specification pins are stipulated for the output pull-up current IPO. These pins cannot be used for input when the CMOS
output specification option is selected.
3. Stipulated for CMOS output specifications with the output N-channel transistor in the off state. (This also applies to P8 when P-channel open drain
is selected.)
4. Stipulated for pull-up output specifications with the output N-channel transistor in the off state.
5. Stipulated for P8 with CMOS output specifications.
6. Stipulated for open drain output specifications with the output N-channel transistor in the off state.
7. Stipulated for open drain output specifications with the output P-channel transistor in the off state.
No. 5003-9/22
LC66556B, 66558B
Parameter
Symbol
Conditions
min
typ
max
Unit
Note
[External clock input conditions]
OSC1: See Figure 1. With the signal input to OSC1
and with OSC2 open (with external clock input
selected for the oscillator circuit option)
Frequency
f
ext
0.4
4.35
MHz
OSC1: See Figure 1. With the signal input to OSC1
and with OSC2 open (with external clock input
selected for the oscillator circuit option)
Pulse width
t
extH
, t
extL
100
ns
OSC1: See Figure 1. With the signal input to OSC1
and with OSC2 open (with external clock input
selected for the oscillator circuit option)
Rise and fall times
t
extR
, t
extF
30
ns
Parameter
Symbol
Conditions
min
typ
max
Unit
Note
I
IH
(1)
P2, P3 (except for the P33/HOLD pin), P6:
V
IN
= 13.5 V, N-channel output, transistor off
P0, P1, P4, P5, P9, PC, OSC1, RES, P33/HOLD
(except for PD, PE, PC2 and PC3):
V
IN
= V
DD
, N-channel output, transistor off
PD, PE, PC2, PC3: V
IN
= V
DD
,
N-channel output, transistor off
5.0
μA
1
Input high level current
I
IH
(2)
1.0
μA
1
I
IH
(3)
1.0
μA
1
I
IL
(1)
Inputs other than PD, PE, PC2, PC3:
V
IN
= V
SS
, N-channel output, transistor off
PC2, PC3, PD, PE:
V
IN
= V
SS
, N-channel output, transistor off
P2, P3 (except for the P33/HOLD pin), P6, P8, P9,
PC: I
OH
= –1 mA
P2, P3 (except for the P33/HOLD pin), P6, P8, P9,
PC: I
OH
= –0.1 mA
P0, P1, P4, P5, P7, PA, PB: I
OH
= –50 μA
–1.0
μA
2
Input low level current
I
IL
(2)
–1.0
μA
2
V
DD
–
1.0
V
OH
(1)
V
3
V
DD
–
0.5
Output high level voltage
V
DD
–
1.0
V
OH
(2)
V
4
P0, P1, P4, P5, P7, PA, PB: I
OH
= –30 μA
V
DD
–
0.5
Output pull-up current
I
PO
P0, P1, P4, P5, P7, PA, PB: V
IN
= V
SS
, V
DD
= 5.5 V
P0, P1, P2, P3, P4, P5, P6, P8, P9, PC
(except for the P33/HOLD pin): I
OL
= 1.6 mA
P7, PA, PB: I
OL
= 8 mA
P2, P3, P6, P7, PA: V
IN
= 13.5 V
(except for P2, P3, P6, P7, P8 and PA): V
IN
= V
DD
P8: V
IN
= V
SS
PD1, PD2, PD3: V
IN
= V
SS
to V
DD
– 1.5 V
PD0: V
IN
= 1.5 V to V
DD
–1.6
mA
4
V
OL
(1)
0.4
V
5
Output low level voltage
V
OL
(2)
I
OFF
(1)
I
OFF
(2)
I
OFF
(3)
V
OFF
(1)
V
OFF
(2)
1.5
V
5.0
μA
6
Output off leakage current
1.0
μA
6
–1.0
μA
7
Comparator offset voltage
±50
±300
mV
±50
±300
mV
[Schmitt characteristics]
Hysteresis voltage
V
HIS
Vt H
0.1 V
DD
V
High level threshold voltage
P2, P3, RES, P6, P9, OSC1, (RC, EXT)
0.5 V
DD
0.2 V
DD
0.8 V
DD
0.5 V
DD
V
Low level threshold voltage
Vt L
V
[Ceramic oscillator]
Oscillator frequency
f
CF
t
CFS
OSC1, OSC2: See Figure 2, 4 MHz
4.0
MHz
Oscillator stabilization time
See Figure 3, 4 MHz
10
ms
Continued on next page.