參數(shù)資料
型號(hào)： LC662308A
廠商： Sanyo Electric Co.,Ltd.
英文描述： Four-Bit Single-Chip Microcontroller with 16 KB of On-Chip OTP PROM
中文描述： 四位單片機(jī)與16 KB的片上微控制器檢察官辦公室胎膜早破
文件頁(yè)數(shù)： 21/28頁(yè)
文件大?。?/td> 205K
代理商： LC662308A
No. 5489-21/28
LC66P5316
Continued on next page.
Instruction code
Affected
status
bits
Mnemonic
Operation
Description
Note
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
[Accumulator manipulation instructions]
CLA
Clear AC
1 0 0 0
0 0 0 0
1
1
AC
←
0
(Equivalent to LAI 0.)
AC
←
(AC) + 6
(Equivalent to ADI 6.)
AC
←
(AC) + 10
(Equivalent to
ADI 0AH.)
CF
←
0
CF
←
1
Clear AC to 0.
ZF
Has a vertical
skip function.
DAA
Decimal adjust AC
in addition
1 1 0 0
0 0 1 0
1 1 1 1
0 1 1 0
2
2
Add six to AC.
ZF
Decimal adjust AC
in subtraction
1 1 0 0
0 0 1 0
1 1 1 1
1 0 1 0
DAS
2
2
Add 10 to AC.
ZF
CLC
Clear CF
0 0 0 1
1 1 1 0
1
1
Clear CF to 0.
CF
STC
Set CF
0 0 0 1
1 1 1 1
1
1
Set CF to 1.
CF
CMA
Complement AC
0 0 0 1
1 0 0 0
1
1
AC
←
(AC)
Take the one’s complement
of AC.
ZF
IA
Increment AC
0 0 0 1
0 1 0 0
1
1
AC
←
(AC) + 1
AC
←
(AC) – 1
AC
3
←
(CF),
ACn
←
(ACn + 1),
CF
←
(AC
0
)
AC
0
←
(CF),
ACn + 1
←
(ACn),
CF
←
(AC
3
)
E
←
(AC)
AC
←
(E)
Increment AC.
ZF, CF
DA
Decrement AC
0 0 1 0
0 1 0 0
1
1
Decrement AC.
ZF, CF
Rotate AC right
through CF
RAR
0 0 0 1
0 0 0 0
1
1
Shift AC (including CF) right.
CF
Rotate AC left
through CF
RAL
0 0 0 0
0 0 0 1
1
1
Shift AC (including CF) left.
CF, ZF
TAE
Transfer AC to E
0 1 0 0
0 1 0 1
1
1
Transfer the contents of AC to E.
TEA
Transfer E to AC
0 1 0 0
0 1 1 0
1
1
Transfer the contents of E to AC.
ZF
XAE
Exchange AC with E
0 1 0 0
0 1 0 0
1
1
(AC)
(E)
Exchange the contents of
AC and E.
[Memory manipulation instructions]
IM
Increment M
0 0 0 1
0 0 1 0
1
1
M (HL)
←
[M (HL)] + 1
M (HL)
←
[M (HL)] – 1
Increment M (HL).
ZF, CF
DM
Decrement M
0 0 1 0
0 0 1 0
1
1
Decrement M (HL).
ZF, CF
IMDR i8
Increment M direct
1 1 0 0
I
7
I
6
I
5
I
4
1 1 0 0
I
7
I
6
I
5
I
4
0 1 1 1
I
3
I
2
I
1
I
0
0 0 1 1
I
3
I
2
I
1
I
0
2
2
M (i8)
←
[M (i8)] + 1
Increment M (i8).
ZF, CF
DMDR i8 Decrement M direct
2
2
M (i8)
←
[M (i8)] – 1
Decrement M (i8).
ZF, CF
SMB t2
Set M data bit
0 0 0 0
1 1 t
1
t
0
1
1
[M (HL), t2]
←
1
Set the bit in M (HL) specified
by t0 and t1 to 1.
RMB t2
Reset M data bit
0 0 1 0
1 1 t
1
t
0
1
1
[M (HL), t2]
←
0
Clear the bit in M (HL)
specified by t0 and t1 to 0.
ZF
[Arithmetic, logic and comparison instructions]
Add the contents of AC and
M (HL) as two’s complement
values and store the result
in AC.
AD
Add M to AC
0 0 0 0
0 1 1 0
1
1
AC
←
(AC) +
[M (HL)]
ZF, CF
Add the contents of AC and
M (i8) as two’s complement
values and store the result
in AC.
ADDR i8 Add M direct to AC
1 1 0 0
I
7
I
6
I
5
I
4
1 0 0 1
I
3
I
2
I
1
I
0
2
2
AC
←
(AC) + [M (i8)]
ZF, CF
Add the contents of AC,
M (HL) and C as two’s
complement values and
store the result in AC.
ADC
Add M to AC with CF
0 0 0 0
0 0 1 0
1
1
AC
←
(AC) +
[M (HL)] + (CF)
ZF, CF
Add the contents of AC and
the immediate data as two’s
complement values and store
the result in AC.
ADI i4
Add immediate data
to AC
1 1 0 0
0 0 1 0
1 1 1 1
I
3
I
2
I
1
I
0
2
2
AC
←
(AC) +
I
3
, I
2
, I
1
, I
0
ZF
Subtract the contents of AC
and CF from M (HL) as two’s
complement values and store
the result in AC.
CF will be zero if
there was a
borrow and one
otherwise.
SUBC
Subtract AC from M
with CF
0 0 0 1
0 1 1 1
1
1
AC
←
[M (HL)] –
(AC) – (CF)
ZF, CF
And M with AC then
store AC
AC
←
(AC)
[M (HL)]
Take the logical and of AC
and M (HL) and store the
result in AC.
ANDA
0 0 0 0
0 1 1 1
1
1
ZF
Or M with AC then
store AC
AC
←
(AC)
[M (HL)]
Take the logical or of AC and
M (HL) and store the result
in AC.
ORA
0 0 0 0
0 1 0 1
1
1
ZF
N
b
N
c
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