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參數(shù)資料
| 型號： | LC65F1306A* |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 文件頁數(shù)： | 15/22頁 |
| 文件大?。?/td> | 685K |
LC65F1306A
No.6829-15/22
Ratings
typ.
Parameter
Symbol
Conditions
VDD[V]
Applicable
pins and notes
PE0
PE0
min.
max.
unit
Pulse output
Period
High level pulse
width
tPCY
tPH
tPL
64
×
TCYC
32
×
TCYC
±
10%
32
×
TCYC
±
10%
Low level pulse
width
Fig.7
TCYC=4
×
system clock
Select only Nch OD
option,
and add external 1k
resistor and external 50pF
capacitor.
AV
+
=VDD
AV
-
=VSS
When AD speed is
1/1=26*TCYC
PE0
μ
s
Resolution
Absolute
precision
Conversion
time
8
±
1
±
2
bit
LSB
24
(TCYC=
0.92
μ
s)
47
(TCYC=
0.92
μ
s)
VSS
260
(TCYC=
10
μ
510
(TCYC=
10
μ
s)
VDD
TCAD
When AD speed is
1/2=51*TCYC
μ
s
Analog input
voltage range
Analog
input current
VAIN
AD0 to AD7
V
Including the output off
leakage current.
VAIN=VDD
VAIN=VSS
1
A
port
IAIN
3 to 5.5
AD0 to AD7
(The shared
I/O function
ports have
open-drain
specification)
WDR
-1
μ
A
Cw
When PE1 is using
open-drain
When PE1 is using
open-drain
When PE1 is using
open-drain
Fig.8
0.1
±
5%
μ
F
Rw
WDR
680
±
1%
k
Recommended
constants
(Note 10)
Rl
WDR
100
±
1%
Clear time
(discharge)
Clear period
(charge)
Recommended
constants
(Note 10)
tWCT
WDR
100
μ
s
tWCCY
Fig.8
3 to 5.5
WDR
36
ms
Cw
When PE1 is using
open-drain
When PE1 is using
open-drain
When PE1 is using
open-drain
Fig.8
WDR
0.01
±
5%
μ
F
Rw
WDR
680
±
1%
k
Rl
WDR
100
±
1%
Clear time
(discharge)
Clear period
(charge)
tWCT
WDR
10
μ
s
W
tWCCY
Fig.8
3 to 5.5
WDR
4.2
ms
Notes:
(1) When oscillated internally under the oscillating conditions in Fig.3, generated voltage can be over the maximum limit of
the VDD.
(2) Average for 100 ms period.
(3) Operating supply voltage VDD must be held until the microcontroller enters in the standby mode after the execution of the
HALT instruction. Any chattering should not be generated at the PA3 pin during the HALT instruction execution cycle.
(4) Recommended circuit constants that are verified by the oscillator manufacturer, using oscillator characteristic evaluation
board selected by SANYO.
(5) The OSC1 pin will have schmitt characteristics when external clock oscillator or the two-pin RC oscillator is selected as
an oscillation option.
(6) These are the results of testing using the value at each part on the Fig.3 circuit which is recommended by SANYO. These
results do not include the current applied to the output transistor, nor the current applied to the transistor with a pull-up
resistor on the LSI.
(7) fCFOSC is the frequency when the values in table 1 are used.
(8) This indicates the elapsed time that is required before the oscillation becomes stable after the VDD exceeds the minimum
limit of the operation supply voltage.
(9) TCYC=4
×
system clock period
(10) When used in an environment that may result in condensation, note that a current leakage between PE1 and adjacent pins
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