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參數(shù)資料
| 型號： | LC65F1306A* |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 文件頁數(shù)： | 10/22頁 |
| 文件大小： | 685K |
LC65F1306A
No.6829-10/22
LC65F1306A Oscillator Options
Circuit type
Frequency
Divider option
(Cycle time)
1/1 (10
μ
s)
VDD
range
3 to 5.5V
Notes
400 kHz
Can not be used with the divide-by-three
and divide-by-four options.
800 kHz
1 MHz
4 MHz
1/1 (5
μ
s)
1/1 (4
μ
s)
1/1 (1
μ
s)
1/3 (3
μ
s)
1/4 (4
μ
s)
1/1 (10.4 to 0.92
μ
s)
1/3 (10.4 to 2.77
μ
s)
1/4 (10.4 to 3.70
μ
s)
3 to 5.5V
3 to 5.5V
3 to 5.5V
3 to 5.5V
3 to 5.5V
3 to 5.5V
3 to 5.5V
3 to 5.5V
3 to 5.5V
Ceramic resonator
External
with
oscillator circuit)
Two-pin RC
clock
2-pin
(used
RC
the
384 k to 4330 kHz
1152 k to 4330 kHz
1536 k to 4330 kHz
Use the no divider circuit option and the
recommended circuit constants. When using
other constants by necessity, use the frequency
and VDD range identical to the external clock
written above.
External clock drive is not possible. To use external clock drive, select the 2-pin RC oscillator option.
External clock used with
the ceramic oscillator
option
Port C and D Output level Option During Reset
The Output level of the C and D ports at reset can be selected from the following two options in 4-bit unit.
Option
Conditions and notes
High level output at reset
Ports C and D in 4-bit unit
Low level output at reset
Ports C and D in 4-bit unit
Port Output Type
The I/O port type is open-drain output.
Option
Open-drain output
Watchdog Reset Option
This option allows the user to select how the PE1/WDR pin is to be used. It can be used as the normal port PE1, or used as the
watchdog reset pin WDR.
Circuit
Ports
Ports A, C, D, E and F
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