
Using Standby HALT Mode
The LC6529N/F/L features a convenient HALT mode that reduces current drain while the chip is on standby.
These standby functions involve the use of one instruction (HALT) and two control signal pins (PA3 and RES). For the
functions to work properly, the design of external circuits and chip software must pay due attention to these three.
Depending on how extensively the standby functions are used, the designer must consider and provide countermeasures
that protect the design from the effects of power supply fluctuations, power interruptions, external noise, and other
adverse conditions.
This document discusses the circuit and program design issues related to the most frequent application of the standby
functions, the detection and recovery from power outages.
When using the standby functions, follow the sample circuits given in this document and carefully observe all warnings
accompanying them.
Departures from the design guidelines herein will warrant thorough testing and evaluation of the effects of such sudden
changes in the operating environment as momentary power outages on application operation.
1. Entering and leaving the HALT mode
Table 1 gives the conditions for entering and leaving the HALT mode.
Table 1 Entering and Leaving the HALT Mode
Note: The second method for leaving the HALT mode is only available when the design uses an RC oscillator circuit. It may not work properly with a ceramic
oscillator circuit.
2. Important notes
Using the standby functions requires close attention to the following issues in application circuit and software design.
The power supply voltage must not fall below the rating while the chip is on standby.
Carefully observe all timing restrictions for the control signals during transitions to and from the HALT mode.
Make sure that a signal for leaving the HALT mode does not overlap the execution of the HALT instruction.
This document demonstrates how to observe these restrictions by discussing both application circuits for a power
failure recovery function and programming considerations.
Such a power failure recovery function detects failure of the main power supply and causes the chip to execute a
HALT instruction to put itself on standby. Reducing the current drain this way allows the backup capacitor to
maintain the register contents for a longer period than otherwise possible. When the power is restored, the chip is
reset and automatically resumes execution with the program counter set to 000H. The following examples discuss
how the software can then distinguish this type of reset from a power on reset sequence along with issues related to
dealing with momentary AC power outages.
Example 1
The first example does not distinguish a power-on reset sequence from a reset trigger by a power failure.
— Circuit diagram
Figure 2-1 gives the circuit diagram for this sample circuit.
No. 5117-33/39
LC6529N, LC6529F, LC6529L
Entering HALT mode
Leaving HALT mode
HALT instruction while PA3 is high.
1. Reset signal (RES pin pulled low.)
2. PA3 pulled low.