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參數(shù)資料
| 型號： | LA76850 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Monolithic Linear IC Black & White Television IC |
| 中文描述： | 單片線性集成電路黑色 |
| 文件頁數(shù)： | 10/31頁 |
| 文件大?。?/td> | 295K |
| 代理商： | LA76850 |
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LA76850
NoA0017-10/31
Continued from preceding page.
Input signal
Symbol
Test point
29
Input signal
Test method
Bus conditions
APC pull-in
range (U), (L)
fPU, fPL
SG4
80dB
μ
Connect an oscilloscope to pin 29 and adjust the
SG4 frequency to a frequency higher than
38.9MHz to bring the PLL into unlocked mode.
(A beat signal appears.) Lower the SG4 frequency
and measure the frequency at which the PLL locks
again. In the same manner, adjust the SG4
frequency to a lower frequency to bring the PLL
into unlocked mode. Higher the SG4 frequency
and measure the frequency at which the PLL locks
again.
Determine the output level difference between
carrier frequencies of 1Mhz, 4.5MHz and 4.8MHz.
(Reference:1MHz)
Determine the output level difference between
carrier frequencies of 1Mhz, 5.5MHz and
5.85MHz. (Reference:1MHz)
Determine the output level difference between
carrier frequencies of 1MHz, 6.0MHz and
6.55MHz. (Reference:1MHz)
Determine the output level difference between
carrier frequencies of 1MHz and 6.5MHz.
(Reference:1MHz)
NT Trap1 (4.5MHz),
2 (4.8MHz)
NTR1
NTR2
SG7
SIF.SYS = "00"
BG Trap1 (5.5MHz),
2 (5.85MHz)
BTR1
BTR2
SG7
SIF.SYS = "01"
I Trap1 (6.0MHz)
2 (6.55MHz)
ITR1
ITR2
SG7
SIF.SYS = "10"
DK Trap1 (6.5MHz)
DTR1
SG7
SIF.SYS = "11"
29
29
29
29
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