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參數(shù)資料
| 型號： | LA42032-E |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 7/7頁 |
| 文件大小： | 0K |
| 描述： | IC AF POWER AMP 5WX2CH SIP13H |
| 標準包裝： | 20 |
| 類型： | AB 類 |
| 輸出類型： | 2 通道（立體聲） |
| 在某負載時最大輸出功率 x 通道數(shù)量： | 5W x 2 @ 8 歐姆 |
| 電源電壓： | 5.5 V ~ 15 V |
| 特點： | 靜音，短路和熱保護，待機 |
| 安裝類型： | 通孔 |
| 供應商設(shè)備封裝： | 13-SIPH |
| 封裝/外殼： | 13-SIP 裸露焊盤 |
| 包裝： | 管件 |
7
INDUSTRIAL TEMPERATURERANGE
IDT72V73260 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
TABLE 4 — INTERNAL REGISTER AND ADDRESS MEMORY MAPPING
TABLE 3 — OUTPUT HIGH-IMPEDANCE CONTROL
TABLE — 1 CONSTANT THROUGHPUT
DELAY VALUE
TABLE 2 — VARIABLE THROUGHPUT
DELAY VALUE
Delay for Constant Throughput Delay Mode
Input Rate
(m – output channel number)
(n – input channel number)
32.768Mb/s
512 + (512 -n) +m time-slots
Delay for Variable Throughput Delay Mode
Input Rate
(m – output channel number; n – input channel number)
m
≤≤≤≤≤ n+2
m > n+2
32.768Mb/s
512 - (n-m) time-slots
(m-n)time-slots
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
R/W
Location
1
STA4
STA3
STA2
STA1
STA0
CH8
CH7
CH6
CH5
CH4
CH3
CH2 CH1 CH0
R
Data Memory
1
0
STA4
STA3
STA2
STA1
STA0
CH8
CH7
CH6
CH5
CH4
CH3
CH2 CH1 CH0
R/W
Connection Memory
0
1
0
x
R/W
ControlRegister
0
1
0
1
x
R
Frame Align Register
0
1
0
x
R/W
Frame Offset Register 0
0
1
0
1
x
R/W
Frame Offset Register 1
0
1
0
1
0
x
R/W
Frame Offset Register 2
0
1
0
1
x
R/W
Frame Offset Register 3
0
1
0
x
R/W
Frame Offset Register 4
0
1
0
1
x
R/W
Frame Offset Register 5
0
1
0
x
R/W
Frame Offset Register 6
0
1
x
R/W
Frame Offset Register 7
Bits MOD1-0 Values in
ODE pin
OSB bit in Control
Output Status
Connection Memory
Register
1 and 1
Don’t Care
Per-channel
high-Impedance
Any, other than 1 and 1
0
high-Impedance
Any, other than 1 and 1
0
1
Enable
Any, other than 1 and 1
1
0
Enable
Any, other than 1 and 1
1
Enable
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LA42032L-E | 制造商:Sony Semiconductor Solutions Division 功能描述: |
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| LA42052HK-E | 制造商:Sony Semiconductor Solutions Division 功能描述: |
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