參數(shù)資料
型號： LA4064ZC-75TN100E
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 42/42頁
文件大小： 0K
描述： IC CPLD 64MACROCELLS 100TQFP
標(biāo)準(zhǔn)包裝： 90
系列： LA-ispMACH
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1)： 7.5ns
電壓電源 - 內(nèi)部： 1.7 V ~ 1.9 V
宏單元數(shù)： 64
輸入/輸出數(shù)： 64
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
9
Table 7. ORP Combinations for I/O Blocks with 16 I/Os
Table 8. ORP Combinations for I/O Blocks with 12 I/Os
ORP Bypass and Fast Output Multiplexers
The ORP bypass and fast-path output multiplexer is a 4:1 multiplexer and allows the 5-PT fast path to bypass the
ORP and be connected directly to the pin with either the regular output or the inverted output. This multiplexer also
allows the register output to bypass the ORP to achieve faster tCO.
Output Enable Routing Multiplexers
The OE Routing Pool provides the corresponding local output enable (OE) product term to the I/O cell.
I/O Cell
The I/O cell contains the following programmable elements: output buffer, input buffer, OE multiplexer and bus
maintenance circuitry. Figure 8 details the I/O cell.
I/O Cell
Available Macrocells
I/O 0
M0, M1, M2, M3, M4, M5, M6, M7
I/O 1
M1, M2, M3, M4, M5, M6, M7, M8
I/O 2
M2, M3, M4, M5, M6, M7, M8, M9
I/O 3
M3, M4, M5, M6, M7, M8, M9, M10
I/O 4
M4, M5, M6, M7, M8, M9, M10, M11
I/O 5
M5, M6, M7, M8, M9, M10, M11, M12
I/O 6
M6, M7, M8, M9, M10, M11, M12, M13
I/O 7
M7, M8, M9, M10, M11, M12, M13, M14
I/O 8
M8, M9, M10, M11, M12, M13, M14, M15
I/O 9
M9, M10, M11, M12, M13, M14, M15, M0
I/O 10
M10, M11, M12, M13, M14, M15, M0, M1
I/O 11
M11, M12, M13, M14, M15, M0, M1, M2
I/O 12
M12, M13, M14, M15, M0, M1, M2, M3
I/O 13
M13, M14, M15, M0, M1, M2, M3, M4
I/O 14
M14, M15, M0, M1, M2, M3, M4, M5
I/O 15
M15, M0, M1, M2, M3, M4, M5, M6
I/O Cell
Available Macrocells
I/O 0
M0, M1, M2, M3, M4, M5, M6, M7
I/O 1
M1, M2, M3, M4, M5, M6, M7, M8
I/O 2
M2, M3, M4, M5, M6, M7, M8, M9
I/O 3
M4, M5, M6, M7, M8, M9, M10, M11
I/O 4
M5, M6, M7, M8, M9, M10, M11, M12
I/O 5
M6, M7, M8, M9, M10, M11, M12, M13
I/O 6
M8, M9, M10, M11, M12, M13, M14, M15
I/O 7
M9, M10, M11, M12, M13, M14, M15, M0
I/O 8
M10, M11, M12, M13, M14, M15, M0, M1
I/O 9
M12, M13, M14, M15, M0, M1, M2, M3
I/O 10
M13, M14, M15, M0, M1, M2, M3, M4
I/O 11
M14, M15, M0, M1, M2, M3, M4, M5
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LA4064ZC-75TN128E 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs
LA4064ZC-75TN144E 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs
LA4064ZC-75TN44E 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs
LA4064ZC-75TN48E 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Auto Grade (AEC-Q100 ) ispMACH4064Z RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LA4064ZV-75TN100E 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs
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