- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄22093 > LA4064ZC-75TN100E (Lattice Semiconductor Corporation)IC CPLD 64MACROCELLS 100TQFP PDF資料下載
參數(shù)資料
| 型號： | LA4064ZC-75TN100E |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 12/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 64MACROCELLS 100TQFP |
| 標準包裝： | 90 |
| 系列： | LA-ispMACH |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 7.5ns |
| 電壓電源 - 內(nèi)部： | 1.7 V ~ 1.9 V |
| 宏單元數(shù)： | 64 |
| 輸入/輸出數(shù)： | 64 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
2
Table 2. LA-ispMACH 4000Z Automotive Family Selection Guide
The LA-ispMACH 4000V/Z automotive family offers densities ranging from 32 to 128 macrocells. There are multiple
density-I/O combinations in Thin Quad Flat Pack (TQFP) packages ranging from 44 to 144 pins. Tables 1 and 2
show the macrocell, package and I/O options, along with other key parameters.
The LA-ispMACH 4000V/Z automotive family has enhanced system integration capabilities. It supports 3.3V (4000V
and 1.8V (4000Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely
driven up to 5.5V when an I/O bank is congured for 3.3V operation, making this family 5V tolerant. The LA-
ispMACH 4000V/Z also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper
latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. The LA-ispMACH 4000V/Z
automotive family is in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1
boundary scan testing capability also allows product testing on automated test equipment. The 1532 interface sig-
nals TCK, TMS, TDI and TDO are referenced to VCC (logic core).
Overview
The LA-ispMACH 4000V/Z automotive devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks
(GLBs) interconnected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O
Blocks (IOBs), which contain multiple I/O cells. This architecture is shown in Figure 1.
Figure 1. Functional Block Diagram
LA-ispMACH 4032Z
LA-ispMACH 4064Z
LA-ispMACH 4128Z
Macrocells
32
64
128
I/O + Dedicated Inputs
32+4
32+4/64+10
64+10
tPD (ns)
7.5
tS (ns)
4.5
tCO (ns)
4.5
fMAX (MHz)
168
Supply Voltage (V)
1.8V
Pins/Package
48-pin Lead-Free TQFP
100-pin Lead-Free TQFP
I/O
Block
ORP
16
GOE0
GOE1
V
CC
GND
TCK
TMS
TDI
TDO
36
Generic
Logic
Block
Generic
Logic
Block
I/O
Block
ORP
16
36
Generic
Logic
Block
Generic
Logic
Block
I/O
Block
I/O
Bank
0
I/O
Bank
1
I/O
Block
36
CLK0/I
CLK1/I
CLK2/I
CLK3/I
16
Global
Routing
P
ool
V
CCO0
GND
V
CCO1
GND
16
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISL61863HIRZ-T | IC USB PWR CTRLR 3A 10DFN |
| ACC36DREH | CONN EDGECARD 72POS .100 EYELET |
| RYM06DTBH | CONN EDGECARD 12POS R/A .156 SLD |
| ISPLSI 2032VE-300LTN44 | IC PLD ISP 32I/O 3NS 44TQFP |
| 5-5583485-6 | CONN TWIN LEAF 3 POS 100 C/L |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LA4064ZC-75TN128E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4064ZC-75TN144E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4064ZC-75TN44E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4064ZC-75TN48E | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Auto Grade (AEC-Q100 ) ispMACH4064Z RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| LA4064ZV-75TN100E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。