參數(shù)資料
型號: L9952GXPTR
廠商: STMICROELECTRONICS
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO36
封裝: LEAD FREE, SSO-36
文件頁數(shù): 9/68頁
文件大小: 859K
代理商: L9952GXPTR
L9952GXP
Description
Doc ID 13518 Rev 5
2.7
Interrupt
Dig_Out4 can be configured via SPI as Interrupt output (INT) by setting Bit 20 /
CR1:INT_enable=’1’.
This configuration will enable the following behaviour:
INT pin is pulled high for 2ms in case of any wake-up from V1 standby mode (WU
inputs, LIN, INH, SPI, open load HS, Iv1 > ICMP_ris)
Wake-up events from V1 standby do not generate a reset (i.e. NRESET is not pulled
low)
The Dig_Out4 settings in CR1 (Bits 12..14) will be ignored
2.8
Cyclic contact supply
In V1 and VBAT - standby mode, any high side driver output (OUT1..4, OUTHS) can be used
to periodically supply external contacts.
The timing is selectable by SPI
Timer 1: period is X sec, the on-time is 10ms resp. 20ms
With X
∈ {0.5, 1.0, 1.5, ... 4 }
Timer 2: period is 50ms, the on- time is 100us resp. 1ms:
Note:
Cyclic sense setup: if cyclic sense feature is used for wake-up inputs (Icxx in control register
2), same input filter timing (Timer1 or Timer2) must be used for HS Outputs (Hsxx in control
register 0).
2.9
Window – watchdog
During normal operation the watchdog monitors the micro controller within a nominal trigger
cycle of 10ms.
In VBAT -standby , V1-standby and Flash program modes, the watchdog circuit is
automatically disabled. However, the watchdog will remain enabled in V1-standby mode
until the current at V1 decreases below ICMP_fall. The V1 current monitoring can be
disabled, if the ICMP bit (CR2, D20) is set to '1'.
After ‘power-on’, ‘standby mode’ or reset, the window watchdog starts with a long open
window (65ms). The long open window allows the micro controller to run its own setup and
then to trigger the watchdog via the SPI. The trigger is finally accepted when the CSN input
becomes HIGH after the transmission of the SPI word.
A correct watchdog trigger will start the window watchdog with a closed window (< 6ms)
followed by an open window (< 10ms), see timing diagrams. Subsequently, the micro
controller has to serve the watchdog by alternating the watchdog trigger bit (CR0, D19). The
“negative” or “positive” edge has to meet the open window time. A correct watchdog trigger
signal will immediately start the next closed window.
After 8 watchdog failures in sequence, the V1 regulator is switched off for 200ms. In case of
7 further watchdog failures, the V1 regulator is completely turned off and the device goes
into VBAT -standby mode until a wakeup occurs. (e.g. via LIN, CAN/INH).
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