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參數(shù)資料
| 型號(hào)： | L9942 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Super Smart Motor Bridge Driver(電機(jī)橋驅(qū)動(dòng)器) |
| 中文描述： | 超級智能電機(jī)橋式驅(qū)動(dòng)器（電機(jī)橋驅(qū)動(dòng)器） |
| 文件頁數(shù)： | 14/21頁 |
| 文件大小： | 160K |
| 代理商： | L9942 |
TIMER1
The interrupt output of TIMER1is connectedto the level sensitive interrupt input I4 of the core (start ad-
dress FF0h). So the interrupthas to be cleared before the interrupt service routine is left.
The autoresetfunction is not implemented.
TIMER1 can get its clock signal from two internaland oneexternal sources(seeFig. 6 and 8).
Internal sources (output mode).
In RUN and WAIT mode the timer is supplied with a clock signal derived from main oscillator. Its fre-
quency is f
MAINCLK
/12. In STOP mode it is supplied with a clock signal derived from standby oscillator
with the frequency f
SBCLK
/12. Therefore the timer can also be operated in STOP mode. A timer interrupt
can finish STOP mode. The max. timer interval is 12 X 2
15
/f. This is 49ms in RUN and WAIT mode for
f
MAINCLK
= 8MHz and 12s in STOP mode for f
SBCLK
= 32kHz.
Externalsource (input mode, input gated mode)
The timer input can be connectedwith I/O port PA2 or oscillator count logic via multiplexer MUX3. This
multiplexer is controlled by bit TEST of oscillator control register OSCR. If this bit is cleared the timer in-
put is connected with PA2 input schmitt trigger. With PA2 configured as input TIMER1 can be operated
in input mode or input gated mode.
If bit TEST of OSCR is set the timer input is connected to output GATE of oscillator count logic. In this
configuration TIMER1 can be operated in input gated mode in order to measure the clock period of RC
oscillatoras described above.
There is no output driver available for TIMER1.
WATCHDOG
The ST6WD1 is used toreset the device after a certain period of time if it is not refreshed.
The watchdog is always active and cannot be disabled. In RUN and WAIT mode of the CPU, when the
main oscillator works, the watchdog is supplied with a clock signal with the frequency f
MAINCLK
/48.
Therefore the period of the watchdog can be programmed in 64 steps from 1.536ms up to 98ms for a
mainclockof 8MHz(see Fig. 5).
In STOP mode of the CPU the watchdog is supplied with a clock signal derived from RC oscillator. It’s
frequency is f
SBCLK
/48. With f
SBCLK
= 32.768kHz the period of the watchdog can be programmed in 64
steps from 375ms up to 24 seconds.
After a reset, ST6WD1 is set to it’s longest period (98msec. for fMAINCLK = 8MHz, in RUN and WAIT
mode; 24 sec in STOP mode).
ST6WD1is able to produce a SW-Reset (bit0 set to ”1”, bit1 to ”0”).
Dataspaceaddress of watchdog registerWDT is D8h.
I/OPort
Pins PA0 ... PA3 are of type IOP4.
The polarityof the interrupt output of the port can be selected by bit PAESin Register BPCR.
If this bit is cleared, the I/O interrupt output is not inverted and an interrupt can be generated on falling
edge or low level (dependingon bit6 of interrupt option register IOR). If this bit is set, interrupts are gen-
erated on rising edge or high level.
If more then one port pin is programmed as interrupt input, overlapping interrupts may occur. This situ-
ation has to be avoidedif edge sensitivity is selected. Otherwise interrupt events might be lost.
Pins PA0 and PA1 may be also used to connect an external line interface circuit with the on-chip CAN
Controller.
Bit BUSIE of the bridge/Port Control Register BPCR (E2H) is used for multiplexing Port A Data Register
bits 0 and 1 with the CAN Module input and output, as shown in Fig. 8.
MICROCONTROLLER SECTION
(continued)
L9942
14/21
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