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參數(shù)資料
| 型號： | L9942 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Super Smart Motor Bridge Driver(電機橋驅(qū)動器) |
| 中文描述： | 超級智能電機橋式驅(qū)動器（電機橋驅(qū)動器） |
| 文件頁數(shù)： | 13/21頁 |
| 文件大?。?/td> | 160K |
| 代理商： | L9942 |
Multiplexer MUX1 is used for test purposes.In normaloperation the 32kHz clock signal is passed to sig-
nal SBCLK. In test mode however (pin TEST=high) the main clock can be supplied to the peripheral
components and the RC oscillator can be stopped by setting bit TEST of oscillator control register
OSCR.
Multiplexer MUX2 is used to select main clockor standby clock for TIMER1 and watchdogunder control
of signal STOP which is active in STOP mode of the CPU.
The RC oscillator is designed to minimize frequency offset caused by temperature, supply voltage,
manufacturingtolerances.Neverthelessthe deviation from 32kHz might be larger than required and tun-
ing will become necessary. For that purposethe RC oscillator frequencycan be measuredand adjusted
under control of the CPU as described in the following (see also fig.7).
The device is in normaloperation mode (pin TEST=low). The standby oscillatoris controlledby oscillator
control register OSCR. Setting bit TEST of OSCR will connect the TIMER1 input with signal GATE via
MUX3. The timer now has to be initialized and programmed to input gated mode. In this mode it will
count clock pulses (f
MAINCLK
±
12) as long as its inputis high. If bit COUNTof OSCRis setnow, the block
COUNT LOGIC generatesone pulse at signal GATE with the length of exactly one period of the RC os-
cillator clock signal. Therefore the timer will count main/oscillator pulses for one period of the standby
clock. At the falling edge of signal GATE bit READY of OSCR is set indicating the end of the measure-
ment. Now the timercan be read by the CPU to determinethe actual frequencyof the standbyoscillator.
Bits TEST,COUNT, READY can be cleared now. As long as COUNT is set, READY can not be cleared
by software.
Timerresolutionat f
MAINCLK
= 8MHz is 12
125ns= 1.5
μ
s.
Measurementof a clockperiod of TGATE= 1/32kHz= 31.3
μ
s thereforeshowsa resolutionof about 5%.
The RC oscillator has a nominal frequency of 32kHz and can be adjusted with frequency control bits
FC2, 1, 0. Adjustment is performed in steps of 4kHz (i. e. 12.5%) from 16kHz to 44kHz as shown in the
following table.
FC2
0
0
0
0
1
1
1
1
FC1
0
0
1
1
0
0
1
1
FC0
0
1
0
1
0
1
0
1
f
RCOSC
/kHz
44
40
36
32
28
24
20
16
Register OSCR is cleared at system reset. Therefore the highest frequencyof RC oscillator is selected.
Bits 5 and6 are not implemented. They are read as zero.
MICROCONTROLLER SECTION
(continued)
SBCLK
COUNT
GATE
READY
TGATE
= 1/fSBCLK
TGATE
Figure 7. Signals of RCoscillator count logic.
L9942
13/21
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