參數(shù)資料
型號(hào)： L9942
廠商： 意法半導(dǎo)體
英文描述： Super Smart Motor Bridge Driver(電機(jī)橋驅(qū)動(dòng)器)
中文描述： 超級(jí)智能電機(jī)橋式驅(qū)動(dòng)器（電機(jī)橋驅(qū)動(dòng)器）
文件頁(yè)數(shù)： 11/21頁(yè)
文件大?。?/td> 160K
代理商： L9942
MICROCONTROLLER SECTION
Battery voltage VS is applied to the contact monitor pin Cn by the sense signal from strobe generator.
The contact current is monitored by the current comparator. If the current is below the threshold level
ICMTH a logic zero is generated, if the current is above I
CMTH
a logic one is generated and sampled in
contact sample register CSR with the strobe signal. The contentof CSR is permanently compared with
the content of contactmonitor compare registerCMCR.
The purpose of this register is to store the last contact status (written by software). Whenever a contact
changes from its previousstate a mismatch between CSR and CMCR will occur and an interrupt is gen-
erated. The controllerhas to readthe contactstatusnow. As CMSR is valid for 30
μ
s duringsensing only
(and this is completely asynchronous to CPU operation) the controller can sense the contact perma-
nently by setting contact monitor biasing register CMBR. If a bit is set the corresponding contact is
sensed permanently and can be read by the CPU via CMSR independently from the dynamic sensing
mechanism.When the CPU has determinedthe contactwhich changed its state the correspondingbit in
CMCR has to be changedin order to clear the interrupt request.
The interrupt lines from all channels are ored and can set the interrupt flagIF in contact monitor interrupt
registerCMIR. This flag can be maskedwith enablebit EN.
When all bits in CMCR and CSR match the interrupt signal INT is cleared and the flag IF can be reset
under softwarecontrol. As long as at least one channel interrupt INTn is active the interrupt flag IF can-
not be clearedas the set function is dominant.
This guarantees that no contact state change can be lost. The interrupt output of the contact monitor is
connected to level sensitive interrupt input #3 of the CPU. Therefore the interrupt has to be cleared be-
forethe interrupt service routine is left.
The CPU controls the operationof the 7 contactmonitors, using 4 registers.
- Statusregister : readonly (one foreach channel)
MSB
bit7
bit7 is always read as zero
CMSR holds the status of those contacts which aredetermined in CMBR to be
sensed permanently. The other bits are not valid and may change randomly.
Set means contact isclosed, Reset means contact is open.
- Interruptregister: 2 bits)
LSB
CS0
CS6
CS5
CS4
CS3
CS2
CS1
CMSR
EN
bit7 is always read as zero
this register is cleared by reset.
IF
n.i.
n.i.
n.i.
n.i.
n.i.
n.i.
CMIR
EN: Interruptenable bit: set/resetby the CPU, enablesor disablesthe ContactMonitor Interrupt.
IF: read/write interrupt flag, set if one statusbit changes,reset by CPU only
- Biasing register: 7 bit register(one for each channel)set/reset by CPU, enablespermanent contact
biasing.Set means contactis permanentlybiased.
bit7
bit7 is always read as zero
this register is cleared by reset.
CB6
CB5
CB4
CB3
CB2
CB1
CB0
CMBR
- Compareregister: 7 bit register(one for each channel)set/resetby CPU.This registeris permanently
comparedwith CSR (strobed contacts)
bit7
bit7 is always read as zero
this register is cleared by reset.
CC6
CC5
CC4
CC3
CC2
CC1
CC0
CMCR
Oscillators
The L9942 has two oscillatorsto provideappropriateclock signalsin RUN and STOP mode (see Fig. 6).
L9942
11/21
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