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參數(shù)資料
| 型號(hào)： | L9929 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | SPI CONTROLLED H-BRIDGE |
| 中文描述： | 可控的SPI H橋 |
| 文件頁(yè)數(shù)： | 8/23頁(yè) |
| 文件大小： | 629K |
| 代理商： | L9929 |
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L9929
8/23
Table 5. Electrical Characteristcs
Symbol
Input SCK
(SPI clock input)
V
SCKL
Low Level
V
SCKH
High Level
V
SCK
Hysteresis
C
SCK
Input Capacity
-I
SCK
Input Current
Parameter
Test Condition
Min.
Typ.
Max.
Unit
1
V
2
V
0.1
0.4
V
10
pF
Pull up current source connected
to V
S
20
50
μ
A
Input SS
(Slave select signal)
V
SSL
Low Level
V
SSH
High Level
V
SS
Hysteresis
C
SS
Input Capacity
-I
SS
Input Current
L9929 is selected
1
V
2
V
0.1
0.4
V
10
pF
Pull up current source connected
to V
S
20
50
μ
A
Input SI
(SPI data input)
V
SIL
Low Level
V
SIH
High Level
V
SI
Hysteresis
C
SI
Input Capacity
-I
SI
Input Current
1
V
2
V
0.1
0.4
V
Guaranteed by design
10
pF
Pull up current source connected
to V
S
20
50
μ
A
Output SO
(Tristate output of the L9929 (SPI output); On active reset (DI) output SO is in tristate.)
V
SOL
Low Level
I
SO
= 2mA
V
SOH
High Level
I
SO
= -2mA
1
V
2
V
C
SO
-I
SO
Input DMS
(Supply-Input for the SPI-Inteface and Selection Pin for SPI- or SF-Mode)
V
i
Input Voltage
Capacity
Capacity of the pin in tristate
10
pF
Leakage Current
In tristate
-10
10
μ
A
SPI-Mode
Status-Flag-Mode
SPI-Mode
4.5
0.8
10
V
V
I
c
Input Current
mA
Timing
t
cyc
t
lead
t
lag
Cycle-Time (1)
200
ns
Enable Lead Time (2)
100
ns
Enable Lag Time (3)
150
ns
t
v
Data Valid CL = 40pF (4)
Data Valid CL = 200pF
(referred to L9929)
Data Setup Time (5)
(referred to master)
Data Hold Time (6)
40
150
ns
ns
t
su
50
ns
t
h
t
dis
20
ns
Disable Time (7)
(referred to L9929)
100
ns
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