參數(shù)資料
型號: L9929
廠商: 意法半導體
英文描述: SPI CONTROLLED H-BRIDGE
中文描述: 可控的SPI H橋
文件頁數(shù): 12/23頁
文件大小: 629K
代理商: L9929
L9929
12/23
Figure 12.
5.2
SPI-Logic and I/O-Pins are alternativ supplied from DMS or Vcc internal, depending on which voltage is higher.
That is why diagnosis of the EN-/DI-Pins is always possible, even in case of missing H-Bridge-power supply e.g.
during Vorlauf/Nauchlauf“.
Power Supply of the SPI-Interface
5.3
1)
Characteristics of the SPI Interface
When DMS is > 3.1V, the SPI is active, independent of the state of EN or DI and the voltage on V
S
. During
active reset conditions (DMS < 2.5V) the SPI is driven into its default state. When reset becomes inactive,
the state machine enters into a waitstate for the next instruction.
If the slave select signal at SS is inactive (high), the state machine is forced to enter the waitstate, i.e. the
state machine waits for the following instruction.
During active (low) state of the select signal SS the falling edge of the serial clock signal SCK will be used
to latch the input data at SI. Output data at SO are driven with the rising edge of SCK. Further processing
of the data according to the instruction ( i.e. modification of internal registers) will be triggered by the rising
edge of the SS signal. (-> See Note)
Chipaddress: In order to establish the option of extended addressing the uppermost two bits of the instruc-
tion-byte ( i.e the first two SI-bits of a Frame ) are reserved to send a chipaddress. To avoid a busconflict
the output SO must stay high impedant during the addressing phase of a frame (i.e. until the addressbits
are recognised as valid chipaddress). This tristate behavior should be realised in any case, regardless
wether the extended addressoption is used or not. If the chipaddress does not match, the according ac-
cess will be ignored and SO remains high impedant for the complete frame regardless which frametype is
applied.
Check byte: Simultaneously to the receipt of an SPI instruction L9929 transmitts a check byte via the out-
put SO to the controller. This byte indicates regular or irregular operation of the SPI. It contains an initial
bitpattern and a flag indicating an invalid instruction of the previous access.
2)
3)
4)
5)
SPI Control:
State Machine
Clock Counter
Control Bits
Parity Generator
SI
SS
Shift Register
DMS
SPI Power Supply
DIA_REG
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