參數(shù)資料
型號(hào)： L8229
廠商： STMICROELECTRONICS
元件分類： 運(yùn)動(dòng)控制電子
英文描述： STEPPER MOTOR CONTROLLER, 1.5 A, PDSO24
封裝： LEAD FREE, SSO-24
文件頁(yè)數(shù)： 15/42頁(yè)
文件大?。?/td> 858K
代理商： L8229
Obsolete
Product(s)
- Obsolete
Product(s)
L8229_0 and L8229_1 modes
L8229
8.1
Serial interface specification
This device, when in L8229_0 or L8229_1 configuration, is managed via a Serial Interface
Port for a total of 16 bits with 4 different words. This port provides an interface between the
chip and external digital ASIC. For the user this port is write-only: assigned read registers
are for test mode purposes only.
The interface consists of 3 signal lines: chip select (nCS, active low), serial clock (SCLK)
and serial data input (SDI).
The digital ASIC initiates a serial transfer by pulling low the chip select line, nCS. Then it
generates 16 clock pulses on SCLK while presenting the serial data on input SDI. The data
is shifted into the L8229 on the rising edge of SCLK. The digital ASIC presents the data on
SDI one setup time (Tdsu) before the rising edge of SCLK. The data is held constant for the
data hold time (Tdhd) beyond the SCLK rising edge. The less significant bit, or LSB, is the
first to be shifted out of the digital ASIC and into the chip, followed by the remaining bits. The
last of the 16 bits is the most significant bit or MSB. SDI will remain at the value presented
with the last bit of data. The nCS line is then returned to a high state. The low to high
transition of nCS loads the data into the internal L8229 input register where all the inputs are
presented to their appropriate functions in a parallel mode.
In the event that there are less or more than 16 SCLK rising edges during nCS=0, the device
will interprete the packet as invalid. This enables the SPI bus to be shared with others
devices with similar packet skipping functionality (and with programming word length
different from 16 bits), without the use of nCS.
The outputs of the serial input port shall not "glitch" during any operation.
The serial interface is cleared by nRESET signal applied to pin 14. When nRESET=0,
output stages are in Hi-Z mode (all outputs off). Please note that neither TSD nor OCD reset
the SPI.
Table 15.
DC Specifications
(0°C
≤ T
j ≤ 125°C, VS = 32 V, unless otherwise specified)
Name
Description
Conditions
Min
Typ
Max
Units
Vref voltage
Internal reference voltage
1.94
2
2.06
V
Ioff-rev
Reverse current detection offset
(in Active Sync recirculation)
±50
mA
Table 16.
AC/Transient Specifications
(0°C
≤ T
j ≤ 125°C, VS = 32 V, unless otherwise specified)
Name
Description
Conditions
Min
Typ
Max
Units
Osc
Oscillator frequency
4
MHz
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