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L6918 L6918A
4/35
13
ISEN1
Channel 1 current sense pin. The output current may be sensed across a sense resistor or
across the low-side mosfet RdsON. This pin has to be connected to the low-side mosfet drain
or to the sense resistor through a resistor Rg in order to program the current intervention for
each phase at 140% as follow:
Where 35
A is the current offset information relative to the Over Current condition (offset at
OC threshold minus offset at zero load).The net connecting the pin to the sense point must be
routed as close as possible to the PGNDS1 net in order to couple in common mode any
picked-up noise.
14
PGNDS1
Channel 1 Power Ground sense pin. The net connecting the pin to the sense point must be routed as
close as possible to the ISEN1 net in order to couple in common mode any picked-up noise.
15
PGNDS2
Channel 2 Power Ground sense pin. The net connecting the pin to the sense point must be
routed as close as possible to the ISEN2 net in order to couple in common mode any picked-
up noise.
16
ISEN2
Channel 2 current sense pin. The output current may be sensed across a sense resistor or
across the low-side mosfet RdsON. This pin has to be connected to the low-side mosfet drain
or to the sense resistor through a resistor Rg in order to program the current intervention for
each phase at 140% as follow:
Where 35
A is the current offset information relative to the Over Current condition (offset at
OC threshold minus offset at zero load).
The net connecting the pin to the sense point must be routed as close as possible to the
PGNDS2 net in order to couple in common mode any picked-up noise.
17
OSC/INH
FAULT
Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the
external frequency is increased according to the equation:
Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according
to the equation:
If the pin is not connected, the switching frequency is 300KHz.
Forcing the pin to a voltage lower than 0.8V, the device stop operation and enter the inhibit
state; all mosfets are turned OFF.
18
to
22
VID0-4
Voltage Identification pins. These input are internally pulled-up and TTL compatible. They are
used to program the output voltage as specified in Table 1 and to set the over voltage and
power good thresholds.
Connect to GND to program a ‘0’ while leave floating to program a ‘1’.
23
PGOOD
This pin is an open collector output and is pulled low if the output voltage is not within the
above specified thresholds. It must be connected with the Slave’s PGOOD pin.
If not used may be left floating.
24
BOOT2
Channel 2 bootstrap capacitor pin. This pin supplies the high side driver. Connect through a
capacitor to the PHASE2 pin and through a diode to Vcc (cathode vs. boot).
25
UGATE2
Channel 2 high side gate driver output.
26
PHASE2
This pin is connected to the source of the upper mosfet and provides the return path for the
high side driver of channel 2.
27
LGATE2
Channel 2 low side gate driver output.
28
PGND
Power ground pin. This pin is common to both sections and it must be connected through the closest
path to the low side mosfets source pins in order to reduce the noise injection into the device.
L6918A (MASTER) PIN FUNCTION (continued)
N.
Name
Description
I
OCPx
35
AR
g
R
sense
--------------------------
=
I
OCPx
35
AR
g
R
sense
--------------------------
=
f
S
300KHz
14.82 10
6
R
OSC K
()
-----------------------------
+
=
f
S
300KHz
12.91 10
7
R
OSC K
()
-----------------------------
+
=