
L6917
12/27
Figure 5. HICCUP Mode (left) and OCP threshold and Current information (right)
The over current threshold for each phase is set when IINFOx =35A. Since the over current detection gives
origin to Hiccup cycles (and the output voltage goes down to zero, with information losses for the microproces-
sor) the over current threshold must be greater than the nominal current.
Placing the OC threshold at +40% gives a margin to sustain the heavy load transient issued by the processor.
As a consequence, the transconductance resistor Rg has to be designed in order to have current information of
35
A at 140% of the nominal load, corresponding to 25A at nominal load. Considering the feedback current
(IFB), this will be equal to 50A at nominal load and 70A at over current threshold as shown in figure 5.
Since the device is able to read negative current, negative current limit is also provided and it is set when IINFOx
= -12.5
A , corresponding to -50% of the full nominal current. No current is sunk from the FB pin in this condition.
According to the above relationship, the positive limiting current (ILIM_POS) for each phase, which has to be
placed at one half of the total delivered maximum current and the limiting negative current (ILIM_NEG), results:
When over current is detected, all mosfets are turned OFF, the device waits for 2048 clock cycles and another
soft-start is implemented. Over Current is always active, also during soft-start. After three Over Current event,
the condition is latched and the device stops working; Vcc turn OFF and ON is required to restart device oper-
ation.
Over current is set anyway when IINFOx reaches 35A. The full load value is only a convention to work with con-
venient values for IFB. Since the OPC intervention threshold is fixed, to modify the percentage with respect to
the load value, it can be simply considered that, for example, to have on OCP threshold of 170%, this will cor-
respond to IINFOx =35A(IFB =70A). The full load current will then correspond to IINFOx = 20.5A(IFB =41A).
Over current is managed as an under voltage: after a combination of three of then, the device latches the con-
dition and the FAULT pin is driven high.
The full differential path helps the designer to place sensing element where wanted. Transconductance Rg re-
sistors must be placed as close as possible to ISENx and PGNDSx pins in order to reject noise from the device.
Keeping the traces parallel and guarded by a power plane results in common mode coupling for any picked-up
noise.
IFB
IOUT
2x35A=70
A
2x25
A=50A
140%
100%
-50%
IINFOx
35
A
25
A
-12.5
A
IOUT
Hiccup Mode:
CH1 = FAULT; CH2 = VOUT; CH3 = IL1;CH4 = IL2
I
L IM_POS
35
ARg
R
SENSE
---------------------------
I
LIM_NEG
12.5
–
ARg
R
SE NS E
-----------------------------------
Rg
I
LIM RSENS E
35
A
-------------------------------------
=