參數(shù)資料
型號: L6728D
廠商: STMICROELECTRONICS
元件分類: 穩(wěn)壓器
英文描述: 30 A SWITCHING CONTROLLER, 300 kHz SWITCHING FREQ-MAX, PDSO10
封裝: 3 X 3 MM, ROHS COMPLIANT, DFN-10
文件頁數(shù): 14/33頁
文件大?。?/td> 1215K
代理商: L6728D
L6728D
Application information
Doc ID 16498 Rev 1
21/33
11.2
Output capacitor(s)
The output capacitors are basic components to define the ripple voltage across the output
and for the fast transient response of the power supply. They depend on the output voltage
ripple requirements, as well as any output voltage deviation requirement during a load
transient.
During steady-state conditions, the output voltage ripple is influenced by both the ESR and
capacitive value of the output capacitors as follow:
Where
ΔI
L is the inductor current ripple. In particular, the expression that defines ΔVOUT_C
takes into consideration the output capacitor charge and discharge as a consequence of the
inductor current ripple.
During a load variation, the output capacitor supplies the current to the load or absorbs the
current stored into the inductor until the converter reacts. In fact, even if the controller
immediately recognizes the load transient and sets the duty cycle at 80% or 0%, the current
slope is limited by the inductor value. The output voltage has a drop that, in this case also,
depends on the ESR and capacitive charge/discharge as follows:
Where
ΔV
L is the voltage applied to the inductor during the transient response
(
for the load appliance or VOUT for the load removal).
MLCC capacitors have typically low ESR to minimize the ripple but also have low
capacitances that do not minimize the voltage deviation during dynamic load variations. On
the contrary, electrolytic capacitors have big capacitances to minimize voltage deviation
during load transients, while they do not show the same ESR values of the MLCC resulting
then in higher ripple voltages. For these reasons, a mix between electrolytic and MLCC
capacitor is suggested to minimize ripple and reduce voltage deviation in dynamic mode.
11.3
Input capacitors
The input capacitor bank is designed considering mainly the input RMS current, which
depends on the output deliverable current (IOUT) and the duty cycle (D) for regulation as
follows:
The equation reaches its maximum value, IOUT/2, with D = 0.5. The losses depend on the
input capacitor’s ESR and, in the worst case, are:
ΔV
OUT_ESR
ΔI
L
ESR
=
ΔV
OUT_C
ΔI
L
1
8C
OUT
F
SW
---------------------------------------
=
ΔV
OUT_ESR
ΔI
OUT
ESR
=
ΔV
OUT_C
ΔI
OUT
L
ΔI
OUT
2C
OUT
ΔV
L
--------------------------------------
=
D
MAX
V
IN
V
OUT
I
rms
I
OUT
D1
D
()
=
PESR
I
OUT 2
()
2
=
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