參數(shù)資料
型號: L6701
廠商: 意法半導(dǎo)體
英文描述: 3 Phase Controller for VR10, VR9 and K8 CPUs
中文描述: 3 VR10,VR9和K8處理器相控制器
文件頁數(shù): 37/44頁
文件大?。?/td> 492K
代理商: L6701
L6701
15 System Control Loop Compensation
37/44
15.1 Compensation Network Guidelines
The Compensation Network design assures to having system response according to the cross-
over frequency selected and to the output filter considered: it is anyway possible to further fine-
tune the compensation network modifying the bandwidth in order to get the best response of
the system as follow (See
Figure 19
):
Increase R
F
to increase the system bandwidth accordingly;
Decrease R
F
to decrease the system bandwidth accordingly;
Increase C
F
to move
ω
F
to low frequencies increasing as a consequence the system
phase margin.
Having the fastest compensation network gives not the confidence to satisfy the requirements
of the load: the inductor still limits the maximum dI/dt that the system can afford. In fact, when a
load transient is applied, the best that the controller can do is to “saturate” the duty cycle to its
maximum (d
MAX
) or minimum (0) value. The output voltage dV/dt is then limited by the inductor
charge / discharge time and by the output capacitance. In particular, the most limiting transition
corresponds to the load removal since the inductor results being discharged only by V
OUT
(while it is charged by d
MAX
V
IN
-V
OUT
during a load appliance).
Referring to
Figure 19
-left, further tuning the Compensation network cannot give any
improvements unless the output filter changes: only modifying the main inductors or the output
capacitance improves the system response.
Figure 19. Best Load Transient achievable (d=0) and R
F
-C
F
impact on Bandwidth.
dB
ω
Z
F
(s)
G
LOOP
(s)
K
ω
LC
=
ω
F
ω
ESR
ω
T
R
F
[dB]
R
F
C
F
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