參數(shù)資料
型號(hào): L6701
廠商: 意法半導(dǎo)體
英文描述: 3 Phase Controller for VR10, VR9 and K8 CPUs
中文描述: 3 VR10,VR9和K8處理器相控制器
文件頁(yè)數(shù): 35/44頁(yè)
文件大?。?/td> 492K
代理商: L6701
L6701
15 System Control Loop Compensation
35/44
15
System Control Loop Compensation
The control loop is composed by the Current Sharing control loop (See
Figure 17
) and the
Average Current Mode control loop. Each loop gives, with a proper gain, the correction to the
PWM in order to minimize the error in its regulation: the Current Sharing control loop equalize
the currents in the inductors while the Average Current Mode control loop fixes the output
voltage equal to the reference programmed by VID.
Figure 17
shows the block diagram of the
system control loop.
The system Control Loop is reported in
Figure 18
. The current information I
DROOP
sourced by
the DROOP pin flows into R
FB
implementing the dependence of the output voltage from the
read current.
Figure 17. Main Control Loop
The system can be modeled with an equivalent single phase converter which only difference is
the equivalent inductor L/3 (where each phase has an L inductor).The Control Loop gain results
(obtained opening the loop after the COMP pin):
PWM Z
s
-------------------------------------------------------------------------------+
=
Where:
is the equivalent output resistance determined by the droop function
(
for fully differential current sense);
Z
P
(s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and
the applied load R
O
;
Z
F
(s) is the compensation network impedance;
Z
L
(s) is the parallel of the three inductor impedance;
A(s) is the error amplifier gain;
L3
L2
L1
PWM3
PWM2
PWM1
4 / 5
Reference
ERROR AMPLIFIER
COMP
FB
Z
F
(s)
Z
F
(s)
I
DROOP
C
OUT
R
OUT
1 / 5
1 / 5
1 / 5
CURRENT SHARING
DUTY CYCLE
CORRECTION
I
INFO1
I
INFO2
I
INFO3
G
LOOP
s
( )
( )
R
Z
s
A s
1
A s
)
Z
P
s
( )
Z
L
s
( )
+
[
]
--------------
1
-----------
+
R
FB
+
R
DROOP
D
-------------
R
FB
=
R
DROOP
3
DCR
R
D
-------------
R
FB
=
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