參數(shù)資料
型號(hào): L6701
廠商: 意法半導(dǎo)體
英文描述: 3 Phase Controller for VR10, VR9 and K8 CPUs
中文描述: 3 VR10,VR9和K8處理器相控制器
文件頁(yè)數(shù): 31/44頁(yè)
文件大?。?/td> 492K
代理商: L6701
L6701
13 Output voltage Monitor and Protections
31/44
Figure 14. Feedback Disconnection
13.5 PGOOD (Only for VR9 and K8 Modes)
It is an open-drain signal set free after the soft-start sequence has finished. It is pulled low
when the output voltage drops below -230mV of the programmed voltage.
13.6 Over Current Protection
Output current in each phase is monitored by L6701 through R
ISEN
and so, programming the
value of these resistors, it is possible to set the OCP to the desired value. The Over Current
threshold has to be programmed to a safe value, in order to be sure that the device doesn't
enter OCP during normal operation of the device. This value must take into consideration also
the extra current needed during the Dynamic VID Transition I
D-VID
and, since the device reads
across MOSFETs R
DS(on)
, the process spread and temperature variations of these sensing
elements. Moreover, since also the internal threshold spreads, the Rg design has to consider
the minimum value I
OCTH(min)
of the threshold as follow:
I
I
OCTH min
where I
OCPx
is the current measured by the current reading circuitry when the device enters
Quasi-Constant-Current.
Since the device reads the current across Low Side MOSFETs, it limits the bottom of the
inductor current entering in constant current until setting UVP as below explained. I
OCPx
must
be calculated starting from the corresponding output current value I
OUT(OCP)
as follow (I
D-VID
must also be considered when D-VID are supported) since the device holds the valley current
information:
I
3
where I
OUT(OCP)
is still the output current value at which the device enters Quasi-Constant-
Current, I
PP
is the inductor current ripple in each phase and I
D-VID
is the additional current
required by D-VID (when applicable). In particular, since the device limits the valley of the
L2
L1
L3
DCR1
DCR2
DCR3
C
D
R
D
R
D
R
D
R
G
PHASE3
PHASE2
PHASE1
V
OUT
I
INFO
CS_DROOP+
CS_DROOP-
FB
I
DROOP
x 3
R
F
C
F
R
FB
COMP
VSEN
FBR
FBG
VID
FB_DISCONNECTED
1V
Rg
)
)
-----------------------------------------------------------------
=
I
OCPx
)
---------------------------
I
2
------------
I
------------------
3
+
=
相關(guān)PDF資料
PDF描述
L6701TR 3 Phase Controller for VR10, VR9 and K8 CPUs
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