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參數(shù)資料
| 型號： | L6239 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 152K |
| 代理商： | L6239 |
The write cycle has a fixed address and data
length. Four bits of address and 12 bits of data
must be clocked in to allow the data to be loaded
into the desired register.
The write cycle is initiated by setting SLOAD and
R/W low. Setting R/W low causes the SDIO line
to be tristated for data input. SLOAD low enables
the internal counter to increment on the rising
edge of SCLK. The addressand data are clocked
into the chip serially on each rising edge of SCLK
as shown above. when both the 4 bits of address
and the 12 bits of the data have been clocked in,
then the address register will be written to with
the provided data.
Setting SLOAD high will clear theinternal logic
and tri-state the SDIO line. This also provides a
way of safely aborting a write by simply forcing
SLOADhigh.
NOTE:
SLOAD must be kept low during the entire duration of the 16 write
clocks.
The read cycle is initiated by setting SLOAD low
and clocking in a valid read address.
Only four bits of address are necessary, if more
than four bits are clocked in, the four MSBs will
be ignored (i.e. only the first four bits will be
used).
If a valid address is detected, the rising edge of
R/W will liad the desired register into the internal
serial/parallel register is then serially clocked out
on every rising edge of SCLK (LSB is clocked out
first). Additional padded bits clocked out will be
zero.
NOTE:
IfSLOAD issetlowwith RWhigh, thecurrentcontents oftheinternal
shift register can be clocked out. This is useful for a ”read back” of
the data last written into the required register.
Figure 3, illustrates the case where the serial port
is deselected while reading data.
During a read mode, the mP is in tri-stateand the
L6239 is writing data on to the SDIO pin. If the
R/W
t
RWS
t
SLS
t
PER
A0
A1
A2
A3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
12 bit address (FIXED)
SLOAD
SCLK
SDIO
4 bit address (FIXED)
t
RWH
t
SLH
D94IN121
t
DS
t
DH
t
AH
t
AS
Figure1:
Serial Write Timing Diagram
R/W
t
RWS
t
RWS
t
PER
A0
A1
A2
A3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
OUTPUT
SLOAD
SCLK
SDIO
INPUT
D94IN122
HiZ
t
RWD
t
SCKD
t
RWH
t
SLS
t
AS
t
AH
Figure2:
Serial Read Timing Diagram
L6239
9/13
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