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參數(shù)資料
| 型號(hào)： | L6239 |
| 文件頁(yè)數(shù)： | 8/13頁(yè) |
| 文件大?。?/td> | 152K |
| 代理商： | L6239 |
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CIRCUIT OPERATION
General
This device includes a sensorless spin driver,
power sequencing with dynamic braking and se-
rial interface for a microprocessor. The device is
register based to eliminate single point intercon-
nects where ever possible.
It is designedto operate with a 12V power supply.
POR
When POR goes low, the L6239 resets itself and
all registers to the ”@POR” state (see register de-
scription).
The L6239 assumes that a separate brake com-
mandmust be issues to brake the spindle.
Serial Interface
The serial interface is designed to be compatible
with the Intel 80196 (and other similar micros) se-
rial interface but is capable of faster data rates,
up to 10MHz.
All read and write operations must consists of 16
bits, with the 80196 this would be two 8 bit ac-
cesses.
The first four bits are address and the next 12 are
data. If the address is a read register, then the
L6239 will use the SCLK from the system to shift
out 12 bitsof data from the addressedregister.
The system must provide 16 SCLK pulses to in-
sure that the read operation completes.The SDIO
lineis capableof driving a 60pf load.
INPUT: A3 - A0
REGISTER
SELECTED
0
1
2
TYPE
0000
0001
0010
WRITE
WRITE
READ
RegisterSelect Table
Symbol
t
RWS
t
SLS
t
RWH
t
SLH
t
SCKD
t
RWD
t
AS
t
DS
t
AH
t
DH
t
SDZ
t
RWZ
t
PER
t
REC
(*)
t
DUT
t
SCLK
Description
Min.
100
Typ.
Max.
Unit
ns
R/W setup time to SCLK going high
SLOAD setup time to SCLK going high
100
ns
R/W hold time after SCLK going high
100
ns
SLOAD hold time after SCLK going high
100
ns
SCLK high to Data Valid
10
30
50
ns
R/W High toData Valid Data bit D [0] valid from HiZ
10
30
50
ns
Address setup time to SCLK going high
30
ns
Data setup time to SCLK going high
30
ns
Address hold after SCLK going high
10
ns
Data hold time after SCLK going high
10
ns
SDIO tri-state after SLOAD going high
30
ns
SDIO tri-state afterR/W going low
30
ns
Minimum SCLK period
100
ns
Recycle - Time between successive accesses
100
ns
Clock duty cycle
40
50
60
%
μ
s
SCLK Clock timing
100
0.1
(*) For 10MHz system clock operation (in other words, 1or more clock cycles of SCLK).
R
/W
1
SLOAD
1
SDIO
DIRECTION
Tri-state
Tri-state (Port un-selected)
0
1
Tri-state (Port un-selected)
Tri-state
0
0
Address/Data input
Input
1
0
Data output
Output
Serial Interface Truth Table
L6239
8/13
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