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參數資料
| 型號： | L6000 |
| 廠商： | 意法半導體 |
| 英文描述： | SINGLE CHIP READ & WRITE CHANNEL |
| 中文描述： | 單芯片讀 |
| 文件頁數： | 5/24頁 |
| 文件大?。?/td> | 279K |
| 代理商： | L6000 |
PIN DESCRIPTION
(continued)
Pin #
OUTPUT
64, 63
Symbol
Type
Description
AGC OUT,
AGC OUT
READ DATA I/O
O
AGC AMPLIFIER OUTPUT: Differential AGC amplifieroutput pins.
29
I/O
READ DATA I/O: Bi-directional TTL pin. Output is active in the servo mode or
when both READ GATE and WRITE GATE aredeasserted. In test mode, this
is a TTL input used to drive the data separator. The TTL input is enabled by
setting RDI in the controlregister CB.
POSITION ERROR SIGNAL: A Position errorsignal of A minus B output which
is referenced to SERVO REF V.
FILTER DIFFERENTIAL NORMAL OUTPUTS: Low pass & boosted filter
output signals. Must be AC coupled to the next stagenominally DATA PATH.
FILTER DIFFERENTIAL DIFFERENTIADED OUTPUTS: Differentiated filter
outputs should be AC coupled to the next stagenominally CLOCK PATH.
ADDRESS MARK DETECT: Tristate output pin with TTL output levels.It is in
its high impedance state when WRITE GATE is asserted. When READ GATE
is asserted and the register bit isset for soft sector, an address mark search is
initiated in the soft sector operation. This output is latched low (true) when an
address mark hasbeen detected. Deasserting pin READ GATE deasserts pin
ADDR MARK DET.
MULTIPLEXEDTEST POINT OUTPUT:An open emitter ECLoutput test point.
The testpoint output is enabled by SettingED in the control registerCB. The
controlling signal is PD_TEST in the control register CA. When PD_TEST is low ,
the test point output is the delayed read data DRD. The posistive edges of this
signal indicate the data bit position. The positive edges of the DRD and VCOREF
outputs can be used to estimate window centering. Thetime jitterof DRD’s
positive edge is an indication of media bit jitter. WhenPD_TEST ishigh the test
point out is thecomparator of the pulse qualifier. The positive edge indicates that
the input signal has exceeded the positive threshold while a negative edge
indicates that the input signal has gone below thenegative threshold. Two external
resistors are required to use thispin. They should beremoved during normal
operation toreduce power dissipation.
NRZ OUTPUT DATA: Tristate ouput pin with TTL output levels. It is in its high
impedance state when READ GATE is deasserted. Read data output when
READ GATE is asserted.
READ REFERENCE CLOCK: TTL output. A multiplexed clock source used by
the controller, see Clocks and Modes. During amode change, no glitches are
generated and no more thanone lost clockpulse will occur. READ REF
CLOCK remains Fout/3 after READ GATE is asserted, until after synchronized
bits are detected.
MULTIPLEXED TEST POINTOUTPUT: An open emitter ECL output test point.
This test point output is enabled by using the same control bit enabling the
MULT TP1 output. When the controlling signal, PD_TEST isdesserted, the test
point output is the VCO reference input (VCOREF) to the phase detector.The
positive edges are phase locked to Delayed Read Data (DRD). The negative
edges of this open emitter output signal indicate the edges of the decode
window. When PD_TEST is high, the test point output represents the state of
the clock comparator in the pulse qualifier. The signal transitions indicate zero
crossing of the differentiated signal from the electronic filter. Two external
resistor are required to use this pin. They should be removed during normal
operation to reduce power dissipation.
WRITE DATA: TTL output. Encoded write data output. The data is
automatically resynchronized (independent of the delay between READ REF
CLOCK and WRITE CLOCK) to the reference clock FSout. Falling edge of the
WRITE DATA is the data edge.
REFERENCE FREQUENCY OUTPUT: An open emitter ECL output test point.
The frequency is the frequency synthesizer output frequency. This output is
enabled by control register CA. Two external resistors are required to use this
pin. They should be removed during normal operation to reduce power
dissipation.
46
POSITION OUT
O
56, 55
FILT NORM OUT,
FILT NORM OUT
FILT DIFF OUT,
FILT DIFF OUT
ADDR MARK DET
O
58, 57
O
28
O
25
MULT TP1
O
21
READ NRZ
OUTPUT
O
27
READ REF CLOCK
0
24
MULT TP2
O
20
WRITE DATA
O
13
FREQ OUT TP
O
L6000
5/24
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相關代理商/技術參數 |
參數描述 |
|---|---|
| L60000 | 制造商:LAUREL ELECTRONICS 功能描述:Laureate 1/8 DIN serial input meter / remote display, universal 85-264 Vac power |
| L60000FR | 制造商:LAUREL ELECTRONICS 功能描述:MULTIFUNCTION COUNTER 制造商:LAUREL ELECTRONICS 功能描述:MULTIFUNCTION COUNTER; No. of Digits / Alpha:6; Digit Height:14.2mm; Panel Cutout Height:45mm; Panel Cutout Width:92mm; Operating Temperature Min:0C; Operating Temperature Max:60C; Character Size:0.56"; Display Font Color:Red ;RoHS Compliant: Yes |
| L60001FR | 制造商:LAUREL ELECTRONICS 功能描述:Laureate 1/8 DIN multi-function counter / timer, universal 85-264 Vac power, no relays, no analog output, RS232 communications, dual pulse inputs for frequency, rate, rotal, or timing. ;RoHS Compliant: Yes |
| L60002 | 制造商:Honeywell Sensing and Control 功能描述: 制造商:SKAN-A-MATIC 功能描述: 制造商:LAUREL ELECTRONICS 功能描述:Laureate 1/8 DIN serial input meter / remote display, universal 85-264 Vac power |
| L60002VF1 | 制造商:LAUREL ELECTRONICS 功能描述:Laureate 1/8 DIN multi-function counter / timer, universal 85-264 Vac power, no |
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