參數(shù)資料
型號(hào)： L6000
廠商： 意法半導(dǎo)體
英文描述： SINGLE CHIP READ & WRITE CHANNEL
中文描述： 單芯片讀
文件頁(yè)數(shù)： 19/24頁(yè)
文件大小： 279K
代理商： L6000
Synthesizer phase comparator. The Frequency
SynthesizerVCO is fed to divide by M+1 counter,
and the counter output is the other phase compa-
rator input.
Thisdevelops the frequency:
Fout
=(
M
+
1
)
(
N
+
1
)
FREF
Note : For the new value in the M and N registers to be transferred
totheirrespectivecounters,theVCO Center FrequencyDAC register
must beloaded withits value. This means thenormal order ofregister
writes to change the FrequencySynthesizer outputfrequency would
be:
1) Write M and/or N register with its ( their) new value ( s ).
2) Write the VCO CenterFrequency register with its new value.
The RREF is choosen to set the frequencyrange
of both the FDSVCO and the DSVCO.
CLOCKSAND MODES
WRITE
GATE
O
O
1
READ
GATE
0
1
0
VCO
REF
Fout/2
DRD
Fout/2
RRC
DECCLK ENCCLK
MODE
Fout/3
VCO/3
Fout/3
Fout/2
VCO/2
Fout/2
Fout/2
Fout/2
Fout/2
IDLE
READ
WRITE
Notes: 1 Until the VCO locks to the new source,the VCO/2 entries
will be FREQ OUT TP/2.
2: Until the VCO locks to the new source, the VCO/3 entries will be
FREQ OUT TP/3
3: WRITEGATE =READ GATE =1 is undefinedand illegal
DataSeparator
The data separator circuit is a complete 1.7 RLL
ENDEC data recovery circuit. In the read mode,
the circuit performs data synchronization, sync
field search and detect, address mark detect,
Read-back clock generation and data decoding.
In the write mode, the circuit converts NRZ data
into the ( 1.7 ) RLL format described in the Table
1, performs write precompensation,generates the
preamble field and inserts address marks as re-
quested.
The data rate used for recovery is determined by
the VCO Center Frequency DAC, otherwise
called the PLL Control DAC and the external re-
sistor RREF connected to the pin DS IREF and
Data Separator GND. The differential filter con-
nected to the pins DATA SEP FLT and DATA
SEP FLT determine the loop gain, bandwidth and
damping.A secondorderfilter is recommendedin
most systems, and the filter will determine the
system characteristics. The phase comparator of
the Data Separator PLL utilizes phase only com-
parisons when locked to the disk data stream,
only making a phase comparison when a data bit
is available. In the frequencycomparison mode, a
phase compare is is done to every VCO transi-
tion. Thislatter is done wheneverthe PLL is pow-
ered on and data is NOT being read from the
disk. By acquiring both phase and frequencylock
to the input reference frequency and utilizing a
zero phase restart technique, VCO transients are
minimized and false lock to READ DATA is elimi-
nated. The two control inputs READ GATE and
WRITE GATE directly switch the operations of
the Data Separator. In addition, there are two fur-
ther submodes split between the Hard Sector
mode of operation and the Soft Sector.Hard Sec-
tor operation is selectedby resettingthe SOFTbit
control B register via the serial interface. The as-
sertion of READ GATE causes the Data Separa-
tor to enter the lock up sequence, and Read
mode. Read mode continues until READ GATE
deassertion. The assertion of
causes the Separator to enter Write mode.
WRITE GATE should not be deasserted until the
last bit is written on the disk. Assertion of BOTH
signals at once is illegal and will lead to unpre-
dictableresults.
WRITE GATE
Figure2:
Normalized block diagram for filter
Normalizedfor
ω
c
= 2
Π
f
c
= 1
A
N
and A
D
are adjustedfor a gain of 2 @ f = 0.67fc
to denormalized the frequencyit is necessaryto substitudes with
s
2
Π
fc
L6000
19/24
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