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參數(shù)資料
| 型號： | L6000 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | SINGLE CHIP READ & WRITE CHANNEL |
| 中文描述： | 單芯片讀 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大小： | 279K |
| 代理商： | L6000 |
patible data pulse. The PD- Test bit of theregister
CA controls this output being active. NORMAL
operation is for this bit to be reset , but for testing
the Data Separatoras an input,it should be set.
ServoDemodulator
When in Servo mode all circuitry not needed to
acquire embedded servo position information is
deactivated, the AGC loop is switched to the
servo BYP capacitor, the READ DATA I/O output
is activated, the SERVOTC RES Servo time con-
stant setting resistor is connected to LEVEL REF
V, and the hysteresis threshold level is set to the
Servo threshold.
Three servo control inputs,
LATCH CAP A, LATCH CAP B, and RESETCAP
A/B
control the servo peak sample and hold
functions. When HOLD SERVO AGC is deas-
serted, the servo charge pump drives the SERVO
BYP hold capacitor. The current magnitude and
direction is determined by the formula :
Ibyp2 = gm1*( Vset-Va ( DIN ) pp-Vb ( DIN ) pp )
where : gm1 = 640 uA/Vpp
Vset = 1.0Vpp
Va/b( DIN ) pp = peak to peak A or B servo pat-
tern signal voltages across DATA PATH and
DATAPATH.
When SERVO GATE is deasserted, there is an
automatic 1 usec break before make switch in an
action before the capacitor on the DATA BYP pin
is reconnected to the AGC gain control.
The POSITION OUT pin outputs a voltage equal
to the difference beetwen HOLD CAP A and
HOLDCAP B referencedto SERVOREF V.
The DATA BYP and SERVO BYP capacitor volt-
ages will be held constant (subject to leakagecur-
rent) during sleep mode, when the respective
HOLD DATA AGC and HOLD SRV AGC signals
are low, and when they are not being used to
control the AGCloop.
Test bits and modes
The FDCT bit in the Control A register forces the
Charge pump into the fast decay (or 0.08 mA cur-
rent) mode. This bit should be set during power
up in a normal system. The PD_Test bit stands
for Pulse Detector Test and should be reset, so
that MULT TP1 outputs Delayed Read Data
(DRD), and MULT TP2 outputs the Data Separa-
tor VCO(divided by two).
ProgrammableActive Filter
The outputs of theAGC Amplifier of the Pulse De-
tector block are normally AC coupled to inputs of
the Active Filter. The low-pass portion of the ac-
tive filter is to bandlimit noise. The FCutoff regis-
ter is used to set the cutoff frequency of this por-
tion. The filter type is a 7 pole 0.05 degree
equiripple linear phase error low-pass. Shaping
response may also be introduced, via the boost
equalizationavailable. This is done to account for
deficienciesin the recording process. The FBoost
register sets the amount and polarity of boosting
the cutoff
frequency
in the Active Filter. The
amount set is contained in the FB register. The
boost is accomplished by a two pole high-pass
feed forward section in parallel with the low-pass
filter. A differentiator is also part of the Active Fil-
ter major block to turn the recovered peaks into
zero crossing. The differentiator is a single pole,
singlezero active type. The Active Filter blockhas
2 outputs. One set is the differential outputs from
the low-pass/equalizationportion. The other set is
the differential outputs of differentiator portion.
Both sets of the outputs have matched delays to
maintain timing integrity when re-entering the
Pulse Detector major block. The currentreference
for the FC and FB DAC is developed off of the EF
IREF input. The recommended value of the resis-
tor at EFIREF is : 12Kohm
±
1% .
The normalized low-pass transfer functionis :
(i.e.
ω
c
= 2
π
fc = 1) are: (see Fig. 2 forreference)
Vnorm
Vi
=(
1
Ks
2
+
0.75928
)
D
(
s
)
AN
The normalized differentiatortransfer functionis :
Vdiff
Vi
=(
1
Ks
2
+
0.75928
)
s
1.16099
D
(
s
)
AD
where D(s) = (1 + s + 1.27936 + s
2
0.75928)
(1 + s 0.52247 + s
2
0.33882)
(1 + s 0.21323 + s
2
0.1862)
(1 + s 1.16099)
AN and AD are adjusted for a gain of 2 at fs =
(2/3)FC.
FrequencySynthesizer
The Frequency Synthesizer block is used to de-
velop source recording frequencies for writing
data in the system. It is Phase Lock Loop based
circuit with divide countersset by registers loaded
from the serial interface. The frequency gener-
ated, Fout, is 3 times the HOST data rate in
Mbits/sec, and is 2 times the CODE data rate of
pulses written on the disks. The resolution of the
frequency is 1%. The filter to the PLL is external,
and fully differential on the pins FREQ SYN FLT
and FREQ SYN FLT. A secondorder filter is rec-
ommended. The Fout frequency is used in Read,
Write and Idle modes as the reference for the
Data Separator PLL. If the ET bit of ControlA reg-
ister is set in these modes the FRE OUT TP pin
will output the Synthesizerclock Fout. Setting this
bit in Read mode is not recommended in order to
reduce jitter and decrease power dissipation. To
set the frequency, the input REFERENCE FIN is
fed to the divide by N+1 counter, and this counter
output is the reference input of the Frequency
L6000
18/24
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