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參數(shù)資料
| 型號： | L5962 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING REGULATOR, PDSO36 |
| 封裝： | ROHS COMPLAINT, SOP-36 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 242K |
| 代理商： | L5962 |
L5962
I2C bus interface
Doc ID 16819 Rev 2
6
I2C bus interface
Data transmission from microprocessor to the L5962 and viceversa takes place through the
2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to
positive supply voltage must be connected).
6.1
Data validity
As shown by Figure 5, the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
6.2
Start and stop conditions
As shown by Figure 6 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH.
6.3
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
6.4
Acknowledge
The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 6). The receiver** the acknowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the SDAline is stable LOW during this clock
pulse.
* Transmitter
–
master (P) when it writes an address to the L5962
–
slave (L5962) when the P reads a data byte from L5962
** Receiver
–
slave (L5962) when the P writes an address to the L5962
–
master (P) when it reads a data byte from L5962
Figure 5.
Data validity on the I2C bus
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
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