參數(shù)資料
型號: L4969MD
廠商: 意法半導(dǎo)體
英文描述: SYSTEM VOLTAGE REGULATOR WITH FAULT TOLERANT LOW SPEED CAN-TRANSCEIVER
中文描述: 系統(tǒng)電壓調(diào)節(jié)器容錯低速的CAN收發(fā)器
文件頁數(shù): 29/35頁
文件大?。?/td> 337K
代理商: L4969MD
29/35
L4969
2.10
ADR 10: BTL Identifier Filter Bittimelogic Control Register
Figure 25.
The total bitlength equals the sum of 1 + PSEG1 + PSEG2 in units of
μ
s.
The location of the sampling point is determined by the length of PSEG1.
At the start of frame (initial recessive to dominant edge) the bitlength counter is reset.
Upon every signal edge the counter will be lengthened or shortened according to location of the transition within
the programmed boundaries of PSEG1 or PSEG2. If the edge lies within PSEG1 additional cycles are inserted
in order to shift the sampling point to a safe location after the settling of the input signal. If the signal transition
is located within PSEG2, this segment will be shortened accordingly with the goal of the next edge to lie at the
beginning of PSEG1.
The amount of cycles one segment is lengthened or shortened is determined by the type of edge (rec -> dom
or dom -> rec) and the programming of TD: The resynchronization jump width will be either set to ‘1’ (dom ->
rec edge) or to 1 + TD (rec -> dom edge).
Note, that the length of one timequanta depends on the offset of the on chip RC-oscillator and therefore on the
accuracy of calibration (see register RCADJ (ADR 3) for details on frequency correction)
PS23
PS22
PS21
PS2
PS13
PS12
PS11
PS10
D11
D0
Dominant to Rezessive
bitlength difference control
t
d
= t
dom
- t
rez
TD3
TD2
TD1
TD0
Phasesegment 1
length configuration
t
PSEG1
= 1us * (1 + PSEG1)
Phasesegment 2
length configuration
t
PSEG2
= 1us * PSEG2
t = 1u
Bittime synchronization mechanism
t
PSEG1
t
PSEG2
Sample Point
99AT0030
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