參數(shù)資料
型號(hào): L4969MD
廠商: 意法半導(dǎo)體
英文描述: SYSTEM VOLTAGE REGULATOR WITH FAULT TOLERANT LOW SPEED CAN-TRANSCEIVER
中文描述: 系統(tǒng)電壓調(diào)節(jié)器容錯(cuò)低速的CAN收發(fā)器
文件頁(yè)數(shù): 16/35頁(yè)
文件大小: 337K
代理商: L4969MD
L4969
16/35
1.10.1General Dataframe Format:
Figure 7.
Data is sampled on the rising edge of the clock and SOUT will change upon SCLK falling. SOUT will show a
copy of SIN for the Address/Command field for initial data path checks. Independent of the command state,
SOUT will show the content of the register addressed. SIN contains either data to be written or arbitrary data
for all other operations. The transaction will be terminated with four bit of data followed by a 4-Bit wide CRC
(Cyclic Redundancy Check) as a result of either SIN related data or calculated automatically on data returned
via SOUT. Here the
μ
C has to provide the correct sequence in order to get the write command activated inside.
A CRC-failure is signalled via NINT. For returned data the CRC can also be used to verify a successful transfer.
1.10.2 Address/Command Field
Figure 8.
The Address/Command field starts with a 2-Bit start sequence consisting of ‘01’. Any other sequence will lead
to a protocol error signalled via the NINT. The addressfield is specifying the register to be accessed. The SPI
command flags allow in addition to the normal read/write operation to clear the Interrupt flag register after read.
SCLK
SOUT
ADR/CMD
Datafield 1 (R)
Datafield 2/CRC (R)
0
7
15
15
SIN
0
ADR/CMD
7
Datafield 1 (W/R)
15
Datafield 2/CRC (W/R)
15
99AT0015
8
8
23
23
ADR2
ADR1
ADR3
1
0
ADR0
C1
C0
7
0
Frame start sequence
always has to be
transmitted as 0 1
Addressfield specifying
the Control/Status word
to be accessed
SPI command:
00: Read register
01: Clear IFR
10: illegal command
11: Write register
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