參數(shù)資料
型號: L4969MD
廠商: 意法半導(dǎo)體
英文描述: SYSTEM VOLTAGE REGULATOR WITH FAULT TOLERANT LOW SPEED CAN-TRANSCEIVER
中文描述: 系統(tǒng)電壓調(diào)節(jié)器容錯(cuò)低速的CAN收發(fā)器
文件頁數(shù): 10/35頁
文件大?。?/td> 337K
代理商: L4969MD
L4969
10/35
1.2
The following state-diagram illustrates the possible mode transitions inside the device.
As a prerequisite, a SPI-connection to the uC with the correct CRC-algorythms is required.
During the debug phase the NRES line can be forced high externally (connect to V1) to deactivate the startup
failure mechanis keeping V1 will alive.
Power-Up, Initialization and Sleep mode transitions
Figure 3.
STARTUP
V1 active
V2, V3, CAN off
t=320ms
STARTUP
FAILURE
RESET low
t=1ms
(fail ++)
fail = 7
FORCED SLEEP
V1 off
No Reset
WAKEUP
V1 Low
WDC-ACK
WDC-ACK
t=t
WIN2
WINDOW
WATCHDOG
REFRESH
WDC-OK
WDC-FAIL
NORMAL MODE
WINDOW WDC
ACTIVE
WND SET
NORMAL MODE
WINDOW WDC
DISABLED
TIMER
ACTIVE
(restart by double
WDC-ACK & WDEN)
WDEN SET
TIMEOUT | WDC-ACK
NRES Low
Programmed
SLEEP
V1 OFF
No Reset
DISAR
SET
DISAR
SET
WAKEUP
WAKEUP&V1_UV
Writing to the WDC-
register
(WDC-ACK)
the NORMAL STATE is
entered.
A missing ACK within 320ms will
initiate a STARTUP FAILURE
phase (RESET low).
If no WDC-ACK is received within
seven retrials the voltage regulator
V1 will be turned off by entering the
FORCED SLEEP state.
Dependig on the value from the last
WDC-ACK, another one has to be
written within the specified time frame
(SWDC[1:0]). A failure will activate
the STARTUP STATE
The Window supervision can temporarily be de-
activated for the time programmed during the
last WDC-ACK (WDT[3:0]). Upon rewriting
(WDC-ACK) or expiry of the timer, the NORMAL
STATE is reentered.
If during the last WDC-ACK WND has been set (after releasing
write lock, see description of Watchdog Control Register) the Win-
dow watchdog is deactivated, and no uC supervision is active.
TIMER
ACTIVE
WDEN SET
(restart by double
WDC-ACK & WDEN)
TIMEOUT | WDC-ACK
Here the timer can be used to
generate time events (i.e.
wakeup uC from stop)
After POR, V1 up or externally forced reset
through low NRES, the STARTUP STATE is
entered
The forced sleep mode is left upon wakeup through either CAN or edge on
WAKE. Applying a permanent wakeup (i.e. both CAN-lines dominant) pre-
vents V1 from being turned off (can be used during System debugging)
Setting DISAR (see Voltage Regulator Control Register) Voltage regulator V1 is
turned off, and the output voltage is decreasing depending on the external load
and blocking capacitor.
Note, that during this transition no Reset will be generated (due to Debugmode).
Upon wakeup howewer NRES will be pulled low, if V1was below the programma-
ble reset threshold (V1_UV).
Forcing NRES high externally, fail will not be incremented (Emulation)
WAKEUP
WDC-ACK
&
WDEN SET
WAKEUP
&V1_UV
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