參數(shù)資料
型號(hào)： KSZ8995XA
廠商： Micrel Inc
文件頁(yè)數(shù)： 33/51頁(yè)
文件大小： 0K
描述： IC SWITCH 10/100 5PORT 128PQFP
標(biāo)準(zhǔn)包裝： 66
系列： *
類型： *
應(yīng)用： *
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 1081 (CN2011-ZH PDF)
配用： 576-1642-ND - BOARD EVALUATION FOR KSZ8995XA
其它名稱： 576-1042
May 2005
39
M9999-051305
KS8995XA
Micrel, Inc.
Register 46 (0x2E): Port 2 Status 0
Register 62 (0x3E): Port 3 Status 0
Register 78 (0x4E): Port 4 Status 0
Register 94 (0x5E): Port 5 Status 0
Address
Name
Description
Mode
Default
7
MDIX status
1 = MDI.
RO
0
0 = MDI-X.
6
AN done
1 = AN done.
RO
0
0 = AN not done.
5
Link good
1 = link good.
RO
0
0 = link not good.
4
Partner flow
1 = link partner flow control capable.
RO
0
control capability
0 = link partner not flow control capable.
3
Partner 100BT
1 = link partner 100BT full-duplex capable.
RO
0
full-duplex capability
0 = link partner not 100BT full-duplex capable.
2
Partner 100BT
1 = link partner 100BT half-duplex capable.
RO
0
half-duplex capability
0 = link partner not 100BT half-duplex capable.
1
Partner 10BT
1 = link partner 10BT full-duplex capable.
RO
0
full-duplex capability
0 = link partner not 10BT full-duplex capable.
0
Partner 10BT
1 = link partner 10BT half-duplex capable.
RO
0
half-duplex capability
0 = link partner not 10BT half-duplex capable.
Register 31 (0x1F): Port 1 Control 14
Register 47 (0x2F): Port 2 Control 14
Register 63 (0x3F): Port 3 Control 14
Register 79 (0x4F): Port 4 Control 14
Register 95 (0x5F): Port 5 Control 14
Address
Name
Description
Mode
Default
7
PHY loopback
1 = perform PHY loopback, i.e. loopback MAC’s Tx
R/W
0
back to Rx.
0 = normal operation.
6
Remote loopback
1 = perform remote loopback, i.e. loopback PHY’s Rx
R/W
0
back to Tx.
0 = normal operation.
5
PHY isolate
1 = electrical isolation of PHY from MII and TX+/TX-.
R/W
0
0 = normal operation.
4
Soft reset
1 = PHY soft reset.
R/W
0
0 = normal operation.
3
Force link
1 = force link in the PHY.
R/W
0
0 = normal operation.
2-1
Reserved
N/A
RO
0
Far end fault
1 = far end fault status detected.
RO
0
0 = no far end fault status detected.
Advanced Control Registers
The IPv4 TOS priority control registers implement a fully decoded 64 bit differentiated services code point (DSCP) register used
to determine priority from the 6 bit TOS field in the IP header. The most significant 6 bits of the TOS field are fully decoded into
64 possibilities, and the singular code that results is compared against the corresponding bit in the DSCP register. If the register
bit is a 1, the priority is high; if it is a 0, the priority is low.
Address
Name
Description
Mode
Default
Register 96 (0x60): TOS Priority Control Register 0
7-0
DSCP[63:56]
R/W
00000000
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