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參數(shù)資料
| 型號(hào)： | KSZ8895MQ |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 63/119頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ETHERNET SW 5PORT 128-PQFP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 控制器類(lèi)型： | 以太網(wǎng)開(kāi)關(guān)控制器 |
| 接口： | MII |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-PQFP（14x20） |
| 包裝： | 托盤(pán) |
| 配用： | 576-3871-ND - BOARD EVALUATION FOR KSZ8895MQ |
| 其它名稱(chēng)： | 576-3753 |
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Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Egress Rate Limit
For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic.
Interframe gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of each
output priority queue is limited by the egress rate specified by the data rate selection table followed the egress rate
limit control registers.
If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in
the output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow
control will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping
at the ingress end, and may be therefore slightly less than the specified egress rate. The egress rate limiting
supports the port-based, 802.1p and DiffServ-based priorities, the port-based priority is fixed priority 0
3 selection by
bits[4
3] of the port register control 0. The 802.1p and DiffServ-based priority can be mapped to priority 03 by
default of the register 128 and 129. In the egress rate limit, set register 135 global control 19 bit 3 for queue-based
rate limit to be enabled if using two-queue or four-queue mode. All related ingress ports and egress port should be
split to two-queue or four-queue mode by the port registers control 9 and control 0. The four-queue mode will use
Q0-Q3 for priority 0
3 by bit[6-0] of the port register egress limit control 14. The two-queue mode will use Q0-Q1 for
priority 0
1by bit[60] of the port register egress limit control 12. The priority levels in the packets of the 802.1p and
DiffServ can be programmed to priority 0
3 by the register 128 and 129 for a re-mapping.
When the egress rate is limited, just use one queue per port for the egress port rate limit. The priority packets will be
based upon the data rate selection table (see Tables 13 and 14). If the egress rate limit uses more than one queue
per port for the egress port rate limit, then the highest priority packets will be based upon the data rate selection table
for the rate limit exact number. Other lower priority packet rates will be limited based upon 8:4:2:1 (default) priority
ratio, which is based on the highest priority rate. The transmit queue priority ratio is programmable.
To reduce congestion, it is good practice to make sure the egress bandwidth exceeds the ingress bandwidth.
Transmit Queue Ratio Programming
In transmit queues 0
3 of the egress port, the default priority ratio is 8:4:2:1. The priority ratio can be programmed by
the port registers control 10, 11, 12 and 13. When the transmit rate exceeds the ratio limit in the transmit queue, the
transmit rate will be limited by the transmit queue 0
3 ratio of the port register control 10, 11, 12 and 13. The highest
priority queue will not be limited. Other lower priority queues will be limited based on the transmit queue ratio.
Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast
Enable Self-address filtering, the unknown unicast packet filtering and forwarding by the Register 131 Global Control
15. Enable Unknown multicast packet filtering and forwarding by the Register 132 Global Control 16.
Enable Unknown VID packet filtering and forwarding by the Register 133 Global Control 17.
Enable Unknown IP multicast packet filtering and forwarding by the Register 134 Global Control 18.
This function is very useful in preventing packets that could degrade the quality of the port in applications such as
voice over Internet Protocol (VoIP) and the daisy chain connection.
Configuration Interface
I
2C Master Serial Bus Configuration
If a 2-wire EEPROM exists, then the KSZ8895MQ/RQ/FMQ can perform more advanced features like broadcast
storm protection and rate control. The EEPROM should have the entire valid configuration data from Register 0 to
Register 255 defined in the “Memory Map,” except the chipID = 0 in the register1 and the status registers. After reset,
the KSZ8895MQ/RQ/FMQ will start to read all 255 registers sequentially from the EEPROM. The configuration
access time (tprgm) is less than 30ms, as shown in Figure 8.
March 12, 2014
48
Revision 1.7
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相關(guān)代理商/技術(shù)參數(shù) |
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| KSZ8895MQ_12 | 制造商:MICREL 制造商全稱(chēng):Micrel Semiconductor 功能描述:Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface |
| KSZ8895MQ-EVAL | 功能描述:以太網(wǎng)開(kāi)發(fā)工具 5-Port 10/100 Ethernet Switch with 1x MII Interface - Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類(lèi)型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類(lèi)型:RMII 工作電源電壓: |
| KSZ8895MQI | 功能描述:以太網(wǎng) IC 5-Port 10/100 Ethernet Switch with 1x MII Interface (Industrial Grade) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8895MQXCA | 功能描述:Ethernet Switch 10/100 Base-T/TX I2C, SPI Interface 128-PQFP (14x20) 制造商:microchip technology 系列:- 包裝:托盤(pán) 零件狀態(tài):有效 協(xié)議:以太網(wǎng) 功能:開(kāi)關(guān) 接口:I2C，SPI 標(biāo)準(zhǔn):10/100 Base-T/TX 電壓 - 電源:1.8V，2.5V，3.3V 電流 - 電源:129mA 工作溫度:0°C ~ 70°C 封裝/外殼:128-BFQFP 供應(yīng)商器件封裝:128-PQFP（14x20） 標(biāo)準(zhǔn)包裝:66 |
| KSZ8895MQXIA | 功能描述:Ethernet Switch 10/100 Base-T/TX I2C, SPI Interface 128-PQFP (14x20) 制造商:microchip technology 系列:- 包裝:托盤(pán) 零件狀態(tài):有效 協(xié)議:以太網(wǎng) 功能:開(kāi)關(guān) 接口:I2C，SPI 標(biāo)準(zhǔn):10/100 Base-T/TX 電壓 - 電源:1.8V，2.5V，3.3V 電流 - 電源:129mA 工作溫度:-40°C ~ 85°C 封裝/外殼:128-BFQFP 供應(yīng)商器件封裝:128-PQFP（14x20） 標(biāo)準(zhǔn)包裝:66 |
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