- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄16827 > KSZ8895MQ-EVAL (Micrel Inc)BOARD EVALUATION FOR KSZ8895MQ PDF資料下載
參數(shù)資料
| 型號(hào)： | KSZ8895MQ-EVAL |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 58/119頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR KSZ8895MQ |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，以太網(wǎng)控制器（PHY 和 MAC） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | KSZ8895MQ |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | 576-3753-ND - IC ETHERNET SW 5PORT 128-PQFP |
| 其它名稱(chēng)： | 576-3871 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)當(dāng)前第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
The KSZ8895MQ/RQ/FMQ provides the option to insert or remove the priority tagged frame's header at each
individual egress port. This header, consisting of the two-byte VLAN Protocol ID (VPID) and the two-byte Tag Control
Information field (TCI), is also referred to as the IEEE 802.1Q VLAN tag.
Tag Insertion is enabled by bit[2] of the port registers control 0 and the port register control 8 to select which source
port (ingress port) PVID can be inserted on the egress port for ports 1, 2, 3, 4 and 5, respectively. At the egress port,
untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in the port
registers control 3 and control 4 for ports 1, 2, 3, 4 and 5, respectively. The KSZ8895MQ/RQ/FMQ will not add tags
to already tagged packets.
Tag Removal is enabled by bit[1] of the port registers control 0 for ports 1, 2, 3, 4 and 5, respectively. At the egress
port, tagged packets will have their 802.1Q VLAN tags removed. The KSZ8895MQ/RQ/FMQ will not modify untagged
packets.
The CRC is recalculated for both tag insertion and tag removal.
802.1p Priority Field Re-mapping is a QoS feature that allows the KSZ8895MQ/RQ/FMQ to set the “User Priority
Ceiling” at any ingress port by the port register control 2 bit 7. If the ingress packet’s priority field has a higher priority
value than the default tag’s priority field of the ingress port, the packet’s priority field is replaced with the default tag’s
priority field.
DiffServ-Based Priority
DiffServ-based priority uses the ToS registers (registers 144 to 159) in the Advanced Control Registers section. The
ToS priority control registers implement a fully decoded, 128-bit Differentiated Services Code Point (DSCP) register
to determine packet priority from the 6-bit ToS field in the IP header. When the most significant six bits of the ToS
field are fully decoded, 64 code points for DSCP result. These are compared with the corresponding bits in the DSCP
register to determine priority.
Spanning Tree Support
Port 5 is the designated port for spanning tree support.
The other ports (Port 1
Port 4) can be configured in one of the five spanning tree states via “transmit enable,”
“receive enable,” and “l(fā)earning disable” register settings in Registers 18, 34, 50, and 66 for Ports 1, 2, 3, and 4,
respectively. The following description shows the port setting and software actions taken for each of the five
spanning tree states:
Disable state: the port should not forward or receive any packets. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1."
Software action: the processor should not send any packets to the port. The switch may still send specific packets to
the processor (packets that match some entries in the static table with “overriding bit” set) and the processor should
discard those packets. Note: the processor is connected to Port 5 via MII interface. Address learning is disabled on
the port in this state.
Blocking state: only packets to the processor are forwarded. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1"
Software action: the processor should not send any packets to the port(s) in this state. The processor should
program the “Static MAC table” with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit
should also be set so that the switch will forward those specific packets to the processor. Address learning is
disabled on the port in this state.
Listening state: only packets to and from the processor are forwarded. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1.
"Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g.
BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the
processor. The processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details.
Address learning is disabled on the port in this state.
Learning state: only packets to and from the processor are forwarded. Learning is enabled.
Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0.”
March 12, 2014
43
Revision 1.7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 202D285-3/42-0 | BOOT MOLDED |
| 0210391086 | CABLE JUMPER 1MM .178M 37POS |
| 202F221-50-0 | BOOT MOLDED |
| 222F274-51-0 | BOOT MOLDED |
| 202A196-25-0 | BOOT MOLDED |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8895MQI | 功能描述:以太網(wǎng) IC 5-Port 10/100 Ethernet Switch with 1x MII Interface (Industrial Grade) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8895MQXCA | 功能描述:Ethernet Switch 10/100 Base-T/TX I2C, SPI Interface 128-PQFP (14x20) 制造商:microchip technology 系列:- 包裝:托盤(pán) 零件狀態(tài):有效 協(xié)議:以太網(wǎng) 功能:開(kāi)關(guān) 接口:I2C，SPI 標(biāo)準(zhǔn):10/100 Base-T/TX 電壓 - 電源:1.8V，2.5V，3.3V 電流 - 電源:129mA 工作溫度:0°C ~ 70°C 封裝/外殼:128-BFQFP 供應(yīng)商器件封裝:128-PQFP（14x20） 標(biāo)準(zhǔn)包裝:66 |
| KSZ8895MQXIA | 功能描述:Ethernet Switch 10/100 Base-T/TX I2C, SPI Interface 128-PQFP (14x20) 制造商:microchip technology 系列:- 包裝:托盤(pán) 零件狀態(tài):有效 協(xié)議:以太網(wǎng) 功能:開(kāi)關(guān) 接口:I2C，SPI 標(biāo)準(zhǔn):10/100 Base-T/TX 電壓 - 電源:1.8V，2.5V，3.3V 電流 - 電源:129mA 工作溫度:-40°C ~ 85°C 封裝/外殼:128-BFQFP 供應(yīng)商器件封裝:128-PQFP（14x20） 標(biāo)準(zhǔn)包裝:66 |
| KSZ8895RQ | 功能描述:以太網(wǎng) IC 5-port Switch, one SW5-RMII and one P5-RMII Interface RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8895RQ TR | 功能描述:以太網(wǎng) IC 5-port Switch, one SW5-RMII and one P5-RMII Interface RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。