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參數(shù)資料
型號(hào): KSZ8895MQ-EVAL
廠商: Micrel Inc
文件頁數(shù): 34/119頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR KSZ8895MQ
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8895MQ
已供物品:
相關(guān)產(chǎn)品: 576-3753-ND - IC ETHERNET SW 5PORT 128-PQFP
其它名稱: 576-3871
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Pin Description (Continued)
Pin Number
Pin Name
Type
(1)
Port
Pin Function
(2)
100
VDDIO
P
3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.
101
LED2-2
IPU/O
2
LED indicator 2.
Strap option for RQ only:
PU (default) = Select the device as clock mode in SW5- RMII,
25MHz crystal/oscillator to X1/X2 pins of the device and pins of
SMRXC and PMRXC output 50MHz clock.
PD = Select the device as normal mode in SW5-RMII. Switch
MAC5 used only. The input clock from X1/X2 pins is not used, the
device’s clock source comes from SMTXC/SMREFCLK pin which
the 50MHz reference clock comes from external 50MHz clock
source, PMRXC can output 50MHz clock for P5-RMII interface in
the normal mode.
102
LED2-1
IPU/O
2
LED indicator 1.
Strap option: for Port 3 only.
PU (default) = Enable auto-negotiation.
PD = Disable auto-negatiation. Strap to register60 bit[7].
103
LED2-0
IPU/O
2
LED indicator 0.
104
LED1-2
IPU/O
1
LED indicator 2.
105
LED1-1
IPU/O
1
LED indicator 1.
Strap option: for port 3 only.
PU (default) = no force flow control, normal operation.
PD = force flow control. Strap to register60 bit[4].
106
LED1-0
IPU/O
1
LED indicator 0.
Strap option for port 3 only.
PU (default) = force half-duplex if auto-negotiation is disabled or
fails.
PD = force full-duplex if auto negotiation is disabled or fails.
Strap to register60 bit[5].
107
MDC
IPU
All
Switch or PHY[5] MII management (MIIM registers) data clock. Or
SMI interface clock
108
MDIO
IPU/O
All
Switch or PHY[5] MII management (MIIM registers) data I/O. Or
SMI interface data I/O.
Features internal pull down to define pin state when not driven.
Note: Need an external pull-up when driven.
109
SPIQ
IPU/O
All
SPI serial data output in SPI slave mode.
Note: Need an external pull-up when driven.
110
SPIC/SCL
IPU/O
All
(1) Input clock up to 25MHz in SPI slave mode,
(2) output clock at 61kHz in I
2C master mode. See “Pin 113.”
Note: Need an external pull-up when driven.
111
SSPID/SDA
IPU/O
All
(1) Serial data input in SPI slave mode;
(2) serial data input/output in I
2C master mode. See “Pin 113.”
Note: Need an external pull-up when driven.
112
SPIS_N
IPU
All
Active low.
(1) SPI data transfer start in SPI slave mode. When SPIS_N is
high, the KSZ8895MQ/RQ/FMQ is deselected and SPIQ is held in
high impedance state, a high-to-low transition to initiate the SPI
data transfer.
(2) not used in I
2C master mode.
March 12, 2014
21
Revision 1.7
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