參數(shù)資料
型號: KSZ8873MLLJ
廠商: Micrel Inc
文件頁數(shù): 71/108頁
文件大?。?/td> 0K
描述: IC ETHERNET SWITCH 3PORT 64LQFP
特色產(chǎn)品: KSZ8873MLLJ Ethernet Switches
標(biāo)準(zhǔn)包裝: 160
系列: *
其它名稱: 576-3996
Micrel, Inc.
KSZ8873MLLJ
September 2011
65
M9999-091911-1.8
Register 31 (0x1F): Port 1 Status 1
Register 47 (0x2F): Port 2 Status 1
Register 63 (0x3F): Port 3 Status 1
Bit
Name
R/W
Description
Default
7
Hp_mdix
R/W
=1, HP Auto MDI/MDI-X mode
=0, Micrel Auto MDI/MDI-X mode
1
Note: Only ports 1 and 2 are
PHY ports.
This bit is not applicable to port
3 (MII).
6
Reserved
RO
Reserved
Do not change the default value.
0
5
Polrvs
RO
=1, Polarity is reversed
=0, Polarity is not reversed
0
Note: This bit is not applicable
to port 3 (MII).
This bit is only valid for 10BT
4
Transmit Flow
Control Enable
RO
=1, Transmit flow control feature is active
=0, Transmit flow control feature is inactive
0
3
Receive Flow
Control Enable
RO
=1, Receive flow control feature is active
=0, Receive flow control feature is inactive
0
2
Operation
Speed
RO
=1, Link speed is 100Mbps
=0, Link speed is 10Mbps
0
1
Operation
Duplex
RO
=1, Link duplex is full
=0, Link duplex is half
0
Reserved
RO
reserved
0
Register 67 (0x43): Reset
Bit
Name
R/W
Description
Default
4
Software
Reset
R/W
=1, Software reset
=0, Clear
Note: Software reset will reset all registers to the initial
values of the power-on reset or warm reset (keep the strap
values).
0
PCS Reset
R/W
=1, PCS reset is used when is doing software reset for a
compelete reset
=0, Clear
Note: PCS reset will reset the state machine and clock
domain in PHY’s PCS layer.
0
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