參數(shù)資料
型號(hào): KSZ8851-16MLL-EVAL
廠商: Micrel Inc
文件頁(yè)數(shù): 74/84頁(yè)
文件大小: 0K
描述: BOARD EVALUATION KSZ8851-16MLL
產(chǎn)品培訓(xùn)模塊: KSZ8851 10/100 Embedded Controllers
標(biāo)準(zhǔn)包裝: 1
系列: LinkMD®
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8851-16MLL
主要屬性: 1 個(gè)端口,100BASE-TX/10BASE-T
次要屬性: 8/16 位接口,LinkMD 線纜診斷
已供物品: 板,文檔
產(chǎn)品目錄頁(yè)面: 1081 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 576-3438-ND - IC CTLR MAC/PHY NON PCI 128PQFP
576-3253-ND - IC CTLR MAC/PHY NON-PCI 128-PQFP
576-3252-ND - IC CTLR MAC/PHY NON-PCI 48-LQFP
其它名稱: 576-3292
PIC16F7X
DS30325B-page 74
2002 Microchip Technology Inc.
Steps to follow when setting up an Asynchronous
Transmission:
1.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 10.1).
2.
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3.
If interrupts are desired, then set enable bit TXIE.
4.
If 9-bit transmission is desired, then set transmit
bit TX9.
5.
Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7.
Load data to the TXREG register (starts
transmission).
8.
If using interrupts, ensure that GIE and PEIE in
the INTCON register are set.
FIGURE 10-2:
ASYNCHRONOUS MASTER TRANSMISSION
FIGURE 10-3:
ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
TABLE 10-5:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
RESETS
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
18h
RCSTA
SPEN
RX9
SREN
CREN
FERR
OERR
RX9D
0000 -00x
19h
TXREG
USART Transmit Register
0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
98h
TXSTA
CSRC
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
0000 -010
99h
SPBRG
Baud Rate Generator Register
0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission.
Note
1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
Word 1
STOP Bit
Word 1
Transmit Shift Reg
START Bit
Bit 0
Bit 1
Bit 7/8
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
Word 1
Word 2
START Bit
STOP Bit START Bit
Transmit Shift Reg.
Word 1
Word 2
Bit 0
Bit 1
Bit 7/8
Bit 0
Note: This timing diagram shows two consecutive transmissions.
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