- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16855 > KSZ8851-16MLL-EVAL (Micrel Inc)BOARD EVALUATION KSZ8851-16MLL PDF資料下載
參數(shù)資料
| 型號(hào)： | KSZ8851-16MLL-EVAL |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 65/84頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION KSZ8851-16MLL |
| 產(chǎn)品培訓(xùn)模塊： | KSZ8851 10/100 Embedded Controllers |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | LinkMD® |
| 主要目的： | 接口，以太網(wǎng)控制器（PHY 和 MAC） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | KSZ8851-16MLL |
| 主要屬性： | 1 個(gè)端口，100BASE-TX/10BASE-T |
| 次要屬性： | 8/16 位接口，LinkMD 線纜診斷 |
| 已供物品： | 板，文檔 |
| 產(chǎn)品目錄頁(yè)面： | 1081 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | 576-3438-ND - IC CTLR MAC/PHY NON PCI 128PQFP 576-3253-ND - IC CTLR MAC/PHY NON-PCI 128-PQFP 576-3252-ND - IC CTLR MAC/PHY NON-PCI 48-LQFP |
| 其它名稱： | 576-3292 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)當(dāng)前第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)
PIC16F7X
DS30325B-page 66
2002 Microchip Technology Inc.
9.3.1.1
Addressing
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condi-
tion, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
The SSPSR register value is loaded into the
SSPBUF register.
b)
The buffer full bit, BF is set.
c)
An ACK pulse is generated.
d)
SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave (Figure 9-7). The five Most Sig-
nificant bits (MSbs) of the first address byte specify if
this is a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write so the slave device will receive the sec-
ond address byte. For a 10-bit address, the first byte
would equal ‘1111 0 A9 A8 0’, where A9 and A8 are
the two MSbs of the address.
The sequence of events for 10-bit address is as fol-
lows, with steps 7 - 9 for slave-transmitter:
1.
Receive first (high) byte of address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
2.
Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
3.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4.
Receive second (low) byte of address (bits
SSPIF, BF, and UA are set).
5.
Update the SSPADD register with the first (high)
byte of address, if match releases SCL line, this
will clear bit UA.
6.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7.
Receive Repeated START condition.
8.
Receive first (high) byte of address (bits SSPIF
and BF are set).
9.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
TABLE 9-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
9.3.1.2
Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON<6>) is set. This is an error
condition due to the user’s firmware.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
Status Bits as Data
Transfer is Received
SSPSR
→ SSPBUF
Generate ACK
Pulse
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
BF
SSPOV
00
Yes
10
No
Yes
11
No
Yes
0
1
No
Yes
Note:
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MLF2012DR15M | INDUCTOR MULTILAYER .15UH 0805 |
| 0210491067 | CABLE JUMPER 1.25MM .203M 35POS |
| MLF2012A4R7M | INDUCTOR MULTILAYER 4.7UH 0805 |
| RNF-100-3/16-BK-STK | HEATSHRINK RNF-100 3/16"X4' BLK |
| EVAL-ADF4158EB1Z | BOARD EVALUATION FOR ADF4158 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8851-16MLL-EVAL | 制造商:Micrel Inc 功能描述:BOARD EVALUATION FOR KSZ8851-16MLL |
| KSZ8851-16MLLI | 功能描述:以太網(wǎng) IC 10/100BT Ethernet MAC + PHY with Generic (8, 16-bit) Bus Interface (I-Temp, Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8851-16MLLI TR | 功能描述:以太網(wǎng) IC 10/100BT Ethernet MAC + PHY with Generic (8, 16-bit) Bus Interface (I-Temp, Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8851-16MLLJ | 功能描述:以太網(wǎng) IC Single-Port Ethernet MAC Controller with 8/16-Bit Non-PCI Interface (125C support) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8851-16MLLJ_10 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。