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參數(shù)資料
| 型號： | KSZ8721SL-EVAL |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 5/33頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR KSZ8721SL |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，以太網(wǎng) PHY |
| 嵌入式： | 否 |
| 已用 IC / 零件： | KSC8721SL |
| 主要屬性： | 1 個(gè)端口，100BASE-TX/100BASE-FX/10BASE-T |
| 次要屬性： | MII，RMII，HP Auto MDI，MDI-X 自動(dòng)極性校正，LinkMD |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | 576-1031-6-ND - IC TXRX PHY 10/100 3.3V 48SSOP KSZ8721SLA4 TR-ND - TRANSCEIVER 10/100 3.3V 48-SSOP 576-1674-5-ND - IC TXRX PHY 10/100 3.3V 48-SSOP KSZ8721SLA4-ND - TXRX 10/100 3.3V 48-SSOP 576-1031-5-ND - IC TXRX PHY 10/100 3.3V 48-SSOP 576-1031-1-ND - IC TXRX PHY 10/100 3.3V 48SSOP 576-1031-2-ND - IC TXRX PHY 10/100 3.3V 48SSOP |
| 其它名稱： | 576-1630 |
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May 2004
13
M9999-051704
KS8721BL/SL
Micrel
asserted. For 10BASE-T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an
end-of-frame (EOF) marker.
Collision: Whenever the line state is half-duplex and the transmitter and receiver are active at the same time, the KS8721BL/
SL asserts its collision signal, which is asynchronous to any clock.
RMII (Reduced MII) Data Interface
RMII interface specifies a low-pin count, Reduced Media Independent Interface (RMII) intended for use between Ethernet
PHYs and Switch or Repeater ASICs. It is fully compliant with IEEE 802.3u [2].
This interface has the following characteristics:
It is capable of supporting 10Mbps and 100Mbps data rates.
A single clock reference is sourced from the MAC to PHY (or from an external source).
It provides independent 2-bit wide (di-bit) transmit and receive data paths.
It uses TTL signal levels compatible with common digital CMOS ASIC processes.
RMII Signal Definition
Direction
Signal Name
(w/respect to the PHY)
(w/respect to the MAC)
Use
REF_CLK
Input
Input or Output
Synchronous clock reference for receive, transmit and
control interface
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data
TX_EN
Input
Output
Transmit Enable
TXD[1:0]
Input
Output
Transmit Data
RX_ER
Output
Input (Not Required)
Receive Error
Reference Clock (REF_CLK)
REF_CLK is a continuous 50MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN, TXD[1:0], and
RX_E. REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide REF_CLK as
an input or an output depending on whether they provide a REF_CLK output or rely on an external clock distribution device.
Each PHY device must have an input corresponding to this clock but may use a single clock input for multiple PHYs
implemented on a single IC.
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is, in
10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 noncontiguous zeroes in 10 bits are detected, the
carrier is detected.
Loss-of-carrier results in the de-assertion of CRS_DV synchronous to REF_CLK. As carrier criteria are met, CRS_DV remains
continuously asserted from the first recovered di-bit of the frame through the final recovered di-bit and is negated prior to the
first REF_CLK that follows the final di-bit.
The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous
relative to REF_CLK, the data on RXD[1:0] remains as “00” until proper receive signal decoding takes place (see “Definition
of RXD[1:0] Behavior”).
Receive Data [1:0] (RXD[1:0])
RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers two
bits of recovered data from the PHY. In some cases (e.g., before data recovery or during error conditions), a predetermined
value for RXD[1:0] is transferred instead of recovered data. RXD[1:0] remains as “00” to indicate idle when CRS_DV is de-
asserted. Values of RXD[1:0] other than “00” when CRS_DV is de-asserted are reserved for out-of-band signalling (to be
defined). Values other than “00” on RXD[1:0] while CRS_DV is de-asserted are ignored by the MAC/repeater. Upon assertion
of CRS_DV, the PHY ensures that RXD[1:0]=00 until proper receive decoding takes place.
Transmit Enable (TX_EN)
Transmit Enable TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] on the RMII for transmission. TX_EN is
asserted synchronously with the first nibble of the preamble and remains asserted while all transmitted di-bits are presented
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8721SLI | 功能描述:以太網(wǎng) IC 10/100 Base-TX/FX Physical Layer Transceiver, Single 3.3V Supply, 48-SSOP (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8721SLI TR | 功能描述:以太網(wǎng) IC 10/100 Base-TX/FX Physical Layer Transceiver, Single 3.3V Supply, 48-SSOP (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8721SL-TR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V Single Power Supply 10/100BASE-TX/FX MII Physical Layer Transceiver |
| KSZ8765CLXCC | 功能描述:Ethernet Switch 10/100 Base-FX/T/TX PHY MII, RMII Interface 80-LQFP (10x10) 制造商:microchip technology 系列:- 包裝:托盤 零件狀態(tài):有效 協(xié)議:以太網(wǎng) 功能:開關(guān) 接口:MII，RMII 標(biāo)準(zhǔn):10/100 Base-FX/T/TX PHY 電壓 - 電源:3.3V 電流 - 電源:- 工作溫度:0°C ~ 70°C 封裝/外殼:80-LQFP 供應(yīng)商器件封裝:80-LQFP（10x10） 標(biāo)準(zhǔn)包裝:160 |
| KSZ8765CLXIC | 功能描述:Ethernet Switch 10/100 Base-FX/T/TX PHY MII, RMII Interface 80-LQFP (10x10) 制造商:microchip technology 系列:- 包裝:托盤 零件狀態(tài):有效 協(xié)議:以太網(wǎng) 功能:開關(guān) 接口:MII，RMII 標(biāo)準(zhǔn):10/100 Base-FX/T/TX PHY 電壓 - 電源:3.3V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 封裝/外殼:80-LQFP 供應(yīng)商器件封裝:80-LQFP（10x10） 標(biāo)準(zhǔn)包裝:160 |
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