Strapping Options(1) Pin Number Pin Name Ty" />
參數(shù)資料
型號(hào)： KSZ8721SL-EVAL
廠商： Micrel Inc
文件頁(yè)數(shù)： 33/33頁(yè)
文件大小： 0K
描述： BOARD EVALUATION FOR KSZ8721SL
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng) PHY
嵌入式： 否
已用 IC / 零件： KSC8721SL
主要屬性： 1 個(gè)端口，100BASE-TX/100BASE-FX/10BASE-T
次要屬性： MII，RMII，HP Auto MDI，MDI-X 自動(dòng)極性校正，LinkMD
已供物品： 板
相關(guān)產(chǎn)品： 576-1031-6-ND - IC TXRX PHY 10/100 3.3V 48SSOP
KSZ8721SLA4 TR-ND - TRANSCEIVER 10/100 3.3V 48-SSOP
576-1674-5-ND - IC TXRX PHY 10/100 3.3V 48-SSOP
KSZ8721SLA4-ND - TXRX 10/100 3.3V 48-SSOP
576-1031-5-ND - IC TXRX PHY 10/100 3.3V 48-SSOP
576-1031-1-ND - IC TXRX PHY 10/100 3.3V 48SSOP
576-1031-2-ND - IC TXRX PHY 10/100 3.3V 48SSOP
其它名稱： 576-1630
May 2004
9
M9999-051704
KS8721BL/SL
Micrel
Strapping Options(1)
Pin Number
Pin Name
Type(2)
Description
6,5,
PHYAD[4:1]/
Ipd/O
PHY Address latched at power-up/reset. The default PHY address is 00001.
4,3
RXD[0:3]
25
PHYAD0/
Ipu/O
INT#
9
PCS_LPBK/
Ipd/O
Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
RXDV
11
ISO/RXER
Ipd/O
Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
21
RMII/COL
Ipd/O
Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
22
RMII_BTB
Ipd/O
Enable RMII back-to-back mode at power-up/reset. PD (default) = Disable,
CRS
PU = Enable.
27
SPD100/
Ipu/O
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)
No FEF/
= 100Mbps. If SPD100 is asserted during power-up/reset, this pin is also latched as
LED1
the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
means no Far_End _Fault.)
28
DUPLEX/
Ipu/O
Latched into Register 0h bit 8 during power-up/reset. PD = Half-duplex, PU
LED2
(default) = Full-duplex. If Duplex is pulled up during reset, this pin is also latched as
the Duplex support in register 4h.
29
NWAYEN/
Ipu/O
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/
LED3
reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
30
PD#
Ipu
Power-Down Enable. PU (default) = Normal operation, PD = Power-Down mode.
Notes:
1. Strap-in is latched during power-up or reset.
2. Ipu = Input w/ internal pull-up.
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.
See “Reference Circuit” section for pull-up/pull-down and float information.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KSZ8721SLI 功能描述:以太網(wǎng) IC 10/100 Base-TX/FX Physical Layer Transceiver, Single 3.3V Supply, 48-SSOP (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8721SLI TR 功能描述:以太網(wǎng) IC 10/100 Base-TX/FX Physical Layer Transceiver, Single 3.3V Supply, 48-SSOP (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8721SL-TR 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V Single Power Supply 10/100BASE-TX/FX MII Physical Layer Transceiver
KSZ8765CLXCC 功能描述:Ethernet Switch 10/100 Base-FX/T/TX PHY MII, RMII Interface 80-LQFP (10x10) 制造商:microchip technology 系列:- 包裝:托盤 零件狀態(tài):有效 協(xié)議:以太網(wǎng) 功能:開關(guān) 接口:MII，RMII 標(biāo)準(zhǔn):10/100 Base-FX/T/TX PHY 電壓 - 電源:3.3V 電流 - 電源:- 工作溫度:0°C ~ 70°C 封裝/外殼:80-LQFP 供應(yīng)商器件封裝:80-LQFP（10x10） 標(biāo)準(zhǔn)包裝:160
KSZ8765CLXIC 功能描述:Ethernet Switch 10/100 Base-FX/T/TX PHY MII, RMII Interface 80-LQFP (10x10) 制造商:microchip technology 系列:- 包裝:托盤 零件狀態(tài):有效 協(xié)議:以太網(wǎng) 功能:開關(guān) 接口:MII，RMII 標(biāo)準(zhǔn):10/100 Base-FX/T/TX PHY 電壓 - 電源:3.3V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 封裝/外殼:80-LQFP 供應(yīng)商器件封裝:80-LQFP（10x10） 標(biāo)準(zhǔn)包裝:160
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