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參數(shù)資料
型號: KSZ8721SL-EVAL
廠商: Micrel Inc
文件頁數(shù): 30/33頁
文件大小: 0K
描述: BOARD EVALUATION FOR KSZ8721SL
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng) PHY
嵌入式:
已用 IC / 零件: KSC8721SL
主要屬性: 1 個端口,100BASE-TX/100BASE-FX/10BASE-T
次要屬性: MII,RMII,HP Auto MDI,MDI-X 自動極性校正,LinkMD
已供物品:
相關(guān)產(chǎn)品: 576-1031-6-ND - IC TXRX PHY 10/100 3.3V 48SSOP
KSZ8721SLA4 TR-ND - TRANSCEIVER 10/100 3.3V 48-SSOP
576-1674-5-ND - IC TXRX PHY 10/100 3.3V 48-SSOP
KSZ8721SLA4-ND - TXRX 10/100 3.3V 48-SSOP
576-1031-5-ND - IC TXRX PHY 10/100 3.3V 48-SSOP
576-1031-1-ND - IC TXRX PHY 10/100 3.3V 48SSOP
576-1031-2-ND - IC TXRX PHY 10/100 3.3V 48SSOP
其它名稱: 576-1630
KS8721BL/SL
Micrel
M9999-051704
6
May 2004
Pin Description
Pin Number
Pin Name
Type(1)
Pin Function
1
MDIO
I/O
Management Independent Interface (MII) Data I/O. This pin requires an external
10K pull-up resistor.
2
MDC
I
MII Clock Input. This pin is synchronous to the MDIO.
3
RXD3/
Ipd/O
MII Receive Data Output. RXD [3..0], these bits are synchronous with RXCLK.
PHYAD
When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII.
RXD [3..0] is invalid when RXDV is de-asserted.
During reset, the pull-up/pull-down value is latched as PHYADDR [1]. See
“Strapping Options” section for details.
4
RXD2/
Ipd/O
MII Receive Data Output.
PHYAD2
During reset, the pull-up/pull-down value is latched as PHYADDR[2]. See
“Strapping Options” section for details.
5
RXD1/
Ipd/O
MII Receive Data Output.
PHYAD3
During reset, the pull-up/pull-down value is latched as PHYADDR [3]. See
“Strapping Options” section for details.
6
RXD0/
Ipd/O
MII Receive Data Output.
PHYAD4
During reset, the pull-up/pull-down value is latched as PHYADDR [4]. See
“Strapping Options” section for details.
7
VDDIO
P
Digital IO 2.5 /3.3V tolerant power supply. 3.3V power Input of voltage
regulator. See “Circuit Design Ref. for Power Supply" section for details.
8
GND
Ground.
9
RXDV/
Ipd/O
MII Receive Data Valid Output.
CRSDV/
During reset, the pull-up/pull-down value is latched as PCS_LPBK. See
PCS_LPBK
“Strapping Options” section for details.
10
RXC
O
MII Receive Clock Output. Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps.
11
RXER/ISO
Ipd/O
MII Receive Error Output.
During reset, the pull-up/pull-down value is latched as ISOLATE during reset. See
“Strapping Options” section for details.
12
GND
Ground.
13
VDDC
P
Digital core 2.5V only power supply. See “Circuit Design Ref. for Power Supply"
section for details.
14
TXER
Ipd
MII Transmit Error Input.
15
TXC/
I/O
MII Transmit Clock Output.
REFCLK
Input for crystal or an external 50MHz clock. When REFCLK pin is used for
REF clock interface, pull up XI to VDDPLL 2.5V via 10k
resistor and leave
XO pin unconnected.
16
TXEN
Ipd
MII Transmit Enable Input.
17
TXD0
Ipd
MII Transmit Data Input.
18
TXD1
Ipd
MII Transmit Data Input.
Notes:
1. P = Power supply.
GND = Ground.
I = Input.
I/O = Bidirectional.
Ipd = Input w/ internal pull-down.
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.
Ipu = Input w/ internal pull-up.
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.
O = Output.
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