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參數(shù)資料
| 型號(hào)： | KSZ8051MLL TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 35/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX PHY 10/T100 3.3V MII 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | PHY 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | MII |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 配用： | 576-3864-ND - BOARD EVALUATION FOR KSZ8051MLL |
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2008 Microchip Technology Inc.
DS22060B-page 43
MCP413X/415X/423X/425X
6.1.4
SERIAL CLOCK (SCK)
(SPI FREQUENCY OF OPERATION)
The SPI interface is specified to operate up to 10 MHz.
The actual clock rate depends on the configuration of
the system and the serial command used. Table 6-1
shows the SCK frequency for different configurations.
TABLE 6-1:
SCK FREQUENCY
6.1.5
THE CS SIGNAL
The Chip Select (CS) signal is used to select the device
and frame a command sequence. To start a command,
or sequence of commands, the CS signal must
transition from the inactive state (VIH) to an active state
(VIL or VIHH).
After the CS signal has gone active, the SDO pin is
driven and the clock bit counter is reset.
If an error condition occurs for an SPI command, then
the Command byte’s Command Error (CMDERR) bit
(on the SDO pin) will be driven low (VIL). To exit the
error condition, the user must take the CS pin to the VIH
level.
When the CS pin returns to the inactive state (VIH) the
SPI module resets (including the address pointer).
While the CS pin is in the inactive state (VIH), the serial
interface is ignored. This allows the Host Controller to
interface to other SPI devices using the same SDI,
SDO, and SCK signals.
The CS pin has an internal pull-up resistor. The resistor
is disabled when the voltage on the CS pin is at the VIL
level. This means that when the CS pin is not driven,
the internal pull-up resistor will pull this signal to the VIH
level.
When the CS pin is driven low (VIL), the
resistance becomes very large to reduce the device
current consumption.
The high voltage capability of the CS pin allows
MCP413X/415X/423X/425X devices to be used in
systems previously designed for the MCP414X/416X/
424X/426X devices.
Memory Type Access
Command
Read
Write,
Increment,
Decrement
Volatile
Memory
SDI, SDO
10 MHz
SDI/SDO(1) 250 kHz (2)
10 MHz
Note 1: MCP41X1 devices only.
2: This is the maximum clock frequency
without an external pull-up resistor.
Note:
There is a required delay after the CS pin
goes active to the 1st edge of the SCK pin.
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| KSZ8051MNL | 功能描述:TXRX PHY 10/T100 3.3V MII 32-QFN RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,140 系列:AU 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):1/1 規(guī)程:CAN 電源電壓:5.3 V ~ 27 V 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SO 包裝:管件 其它名稱:935267940512AU5790D14AU5790D14-ND |
| KSZ8051MNL TR | 功能描述:以太網(wǎng) IC 3.3V, 10Base-T/100Base-TX Physical Layer Transceiver w/ MII Support (32-QFN) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8051MNL-EVAL | 功能描述:以太網(wǎng)開發(fā)工具 3.3V, 10Base-T/100Base-TX Physical Layer Transceiver w/ MII Support (32-QFN) - Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| KSZ8051MNLI | 功能描述:TXRX PHY 10/T100 3.3V 32QFN RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,140 系列:AU 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):1/1 規(guī)程:CAN 電源電壓:5.3 V ~ 27 V 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SO 包裝:管件 其它名稱:935267940512AU5790D14AU5790D14-ND |
| KSZ8051MNLI TR | 功能描述:以太網(wǎng) IC 3.3V, 10Base-T/100Base-TX Physical Layer Transceiver with MII support (32-QFN, Industrial Grade) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
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