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參數(shù)資料
| 型號： | KSZ8051MLL TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 22/48頁 |
| 文件大小： | 0K |
| 描述： | TXRX PHY 10/T100 3.3V MII 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | PHY 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | MII |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 配用： | 576-3864-ND - BOARD EVALUATION FOR KSZ8051MLL |
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2008 Microchip Technology Inc.
DS22060B-page 31
MCP413X/415X/423X/425X
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
Additional descriptions of the device pins follows.
TABLE 3-1:
PINOUT DESCRIPTION FOR THE MCP413X/415X/423X/425X
Pin
Weak
Pull-up/
down (2)
Standard Function
Single
Dual
Symbol
I/O
Buffer
Type
Rheo Pot (1) Rheo
Pot
8L
10L
14L
16L
1
111
16
CS
I
HV w/ST
“smart” SPI Chip Select Input
2
1
SCK
I
HV w/ST
“smart” SPI Clock Input
3
—
3
2
SDI
I
HV w/ST
“smart” SPI Serial Data Input
—
3
—
SDI/SDO
I/O
HV w/ST
“smart” SPI Serial Data Input/Output
4
444
3, 4
VSS
—
P
—
Ground
—
5
P1B
A
Analog
No
Potentiometer 1 Terminal B
—
6
P1W
A
Analog
No
Potentiometer 1 Wiper Terminal
—
7
P1A
A
Analog
No
Potentiometer 1 Terminal A
—
5
—
8
P0A
A
Analog
No
Potentiometer 0 Terminal A
5
6
7
9
P0W
A
Analog
No
Potentiometer 0 Wiper Terminal
6
7
8
10
P0B
A
Analog
No
Potentiometer 0 Terminal B
—
12
13
SHDN
I
HV w/ST
“smart” Hardware Shutdown
7
—
9
13
14
SDO
O
No
SPI Serial Data Out
8
10
14
15
VDD
—
P
—
Positive Power Supply Input
—
11
11,12 NC
—
No Connection
9
11
—
17
EP
—
Exposed Pad (Note 4)
Legend:
HV w/ST = High Voltage tolerant input (with Schmidtt trigger input)
A = Analog pins (Potentiometer terminals)
I = digital input (high Z)
O = digital output
I/O = Input / Output
P = Power
Note 1: The 8-lead Single Potentiometer devices are pin limited so the SDO pin is multiplexed with the SDI pin
(SDI/SDO pin). After the Address/Command (first 6-bits) are received, If a valid Read command has been
requested, the SDO pin starts driving the requested read data onto the SDI/SDO pin.
2: The pin’s “smart” pull-up shuts off while the pin is forced low. This is done to reduce the standby and
shutdown current.
3: The SDO is an open drain output, which uses the internal “smart” pull-up. The SDI input data rate can be
at the maximum SPI frequency. the SDO output data rate will be limited by the “speed” of the pull-up,
customers can increase the rate with external pull-up resistors.
4: The DFN and QFN packages have a contact on the bottom of the package. This contact is conductively
connected to the die substrate, and therefore should be unconnected or connected to the same ground as
the device’s VSS pin.
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| KSZ8051MNL-EVAL | 功能描述:以太網(wǎng)開發(fā)工具 3.3V, 10Base-T/100Base-TX Physical Layer Transceiver w/ MII Support (32-QFN) - Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
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