
MCP47DA1
DS25118C-page 42
2012 Microchip Technology Inc.
FIGURE 5-14:
I2C Read Command Format.
FIGURE 5-15:
I2C Read Communication Behavior.
STOP bit
Slave Address Byte
Command Code
1
01
0
S
11
0
A
00
0
A
Slave Address Byte
Data Byte
AD3
0
D6 D5 D4
D2 D1 D0 A(2) P
Read/Write bit (“0” = Write)
00
0
11
0
1
01
0
1
S = Start Condition
P = Stop Condition
A = Acknowledge
X = Don’t Care
R/W = Read/Write bit
D6:D0 = Data bits
Legend
S
Read/Write bit (“1” = Read)
Note 1: Master Device is responsible for ACK / NACK signal. If a NACK signal occurs, the MCP47DA1 will abort
this transfer and release the bus.
2: The Master Device will Not ACK, and the MCP47DA1 will release the bus so the Master Device can
generate a Stop or Repeated Start condition.
Read 1 Byte with Command Code = 00h
Read 2 Byte with Command Code = 00h
SSlave Address
R
/
W
A
C
K Command Code
A
C
K
R
SSlave Address
R
/
W
A
C
K
Master
S 0 1 011 100 100 000 0001 S 010 111 011
MCP47DA1
0
I2C Bus
S 01 011 100 000 000 0000 S 010 111 010
Data Byte
A
C
KP
Master
1 P
MCP47DA1
0d ddd ddd1
I2C Bus
0 d ddd ddd1 P
SSlave Address
R
/
W
A
C
K Command Code
A
C
K
R
SSlave Address
R
/
W
A
C
K
Master
S 0 1 011 100 100 000 0001 S 010 111 011
MCP47DA1
0
I2C Bus
S 01 011 100 000 000 0000 S 010 111 010
Data Byte
A
C
KData Byte
A
C
KP
Master
0
1 P
MCP47DA1
0d ddd ddd1 0ddd ddd d1
I2C Bus
0 d ddd ddd0 0ddd ddd d1P